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RX5500 (R) 4/15/15 Page 8 of 9
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9 LPFADJ This pin is the receiver low-pass filter bandwidth adjust. The filter bandwidth is set by a resistor R
LPF
between this pin and
ground. The resistor value can range from 330 K to 820 ohms, providing a filter 3 dB bandwidth f
LPF
from 4.5 kHz to 1.8 MHz.
The resistor value is determined by:
R
LPF
= 1445/ f
LPF
, where R
LPF
is in kilohms, and f
LPF
is in kHz
A ±5% resistor should be used to set the filter bandwidth. This will provide a 3 dB filter bandwidth between f
LPF
and 1.3* f
LPF
with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05 degree equiripple phase response.
The peak drive current available from RXDATA increases in proportion to the filter bandwidth setting.
Pin Name Description
10 GND2 GND2 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.
11 RREF RREF is the external reference resistor pin. A 100 K reference resistor is connected between this pin and ground. A ±1%
resistor tolerance is recommended. It is important to keep the total capacitance between ground, Vcc and this node to less
than 5 pF to maintain current source stability. If THLD1 and/or THDL2 are connected to RREF through resistor values less
that 1.5 K, their node capacitance must be added to the RREF node capacitance and the total should not exceed 5 pF.
12 NC This pin should be left unconnected.
13 THLD1 The THLD1 pin sets the threshold for the standard data slicer (DS1) through a resistor R
TH1
to RREF. The threshold is
increased by increasing the resistor value. Connecting this pin directly to RREF provides zero threshold. The acceptable
range for the resistor is 0 to 100 K, providing a THLD1 range of 0 to 90 mV. The resistor value is given by:
R
TH1
= 1.11*V, where R
TH1
is in kilohms and the threshold V is in mV
A ±1% resistor tolerance is recommended for the THLD1 resistor.
14 PRATE The interval between the falling edge of an ON pulse to the first RF amplifier and the rising edge of the next ON pulse to the
first RF amplifier t
PRI
is set by a resistor R
PR
between this pin and ground. The interval t
PRI
can be adjusted between 0.1 and
5 µs with a resistor in the range of 51 K to 2000 K. The value of R
PR
is given by:
R
PR
= 404* t
PRI
+ 10.5, where t
PRI
is in µs, and R
PR
is in kilohms
A ±5% resistor value is recommended. When the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF amplifiers
operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the period t
PRC
from start-to-start
of ON pulses to the first RF amplifier is controlled by the PRATE resistor over a range of 0.1 to 1.1 µs using a resistor of 11 K
to 220 K. In this case the value of R
PR
is given by:
R
PR
= 198* t
PRC
- 8.51, where t
PRC
is in µs and R
PR
is in kilohms
A ±5% resistor value should also be used in this case. Please refer to the ASH Transceiver Designer’s Guide for additional
amplifier duty cycle information. It is important to keep the total capacitance between ground, Vcc and this pin to less than 5
pF to maintain stability.
15 PWIDTH The PWIDTH pin sets the width of the ON pulse to the first RF amplifier t
PW1
with a resistor R
PW
to ground (the ON pulse
width to the second RF amplifier t
PW2
is set at 1.1 times the pulse width to the first RF amplifier). The ON pulse width t
PW1
can be adjusted between 0.55 and 1 µs with a resistor value in the range of 200 K to 390 K. The value of R
PW
is given by:
R
PW
= 404* t
PW1
- 18.6, where t
PW1
is in µs and R
PW
is in kilohms
A ±5% resistor value is recommended. When this pin is connected to Vcc through a 1 M resistor, the RF amplifiers operate at
a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifier ON times are controlled by
the PRATE resistor as described above. It is important to keep the total capacitance between ground, Vcc and this node to
less than 5 pF to maintain stability. When using the high data rate operation with the sleep mode, connect the 1 M resistor
between this pin and CNTRL1 (Pin 17), so this pin is low in the sleep mode.
16 VCC2 VCC2 is the positive supply voltage pin for the receiver RF section. This pin must be bypassed with an RF capacitor, which
may be shared with VCC1. VCC2 must also be bypassed with a 1 to 10 µF tantalum or electrolytic capacitor.
17 CNTRL1 CNTRL1 and CNTRL0 select the receiver modes. CNTRL1 and CNTRL0 both high place the unit in the receive mode.
CNTRL1 and CNTRL0 both low place the unit in the power-down (sleep) mode. CNTRL1 is a high-impedance input (CMOS
compatible). An input voltage of 0 to 300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or greater is inter-
preted as a logic high. An input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic high requires a
maximum source current of 40 µA. Sleep mode requires a maximum sink current of 1 µA. This pin must be held at a logic
level; it cannot be left unconnected.
18 CNTRL0 CNTRL0 is used with CNTRL1 to control the receiver modes. CNTRL0 is a high-impedance input (CMOS compatible). An
input voltage of 0 to 300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or greater is interpreted as a logic
high. An input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic high requires a maximum source
current of 40 µA. Sleep mode requires a maximum sink current of 1 µA. This pin must be held at a logic level; it cannot be left
unconnected.
19 GND3 GND3 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.
20 RFIO RFIO is the receiver RF input pin. This pin is connected directly to the SAW filter transducer. Antennas presenting an imped-
ance in the range of 35 to 72 ohms resistive can be satisfactorily matched to this pin with a series matching coil and a shunt
matching/ESD protection coil. Other antenna impedances can be matched using two or three components. For some imped-
ances, two inductors and a capacitor will be required. A DC path from RFIO to ground is required for ESD protection.
