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9169M-01LF

P1-P3P4-P6P7-P9P10-P10
4
ICS9169-01
Electrical Characteristics at 3.3 V
V
DD
= 3.0 - 3.7 V, T
A
= 0 - 70
o
C unless otherwise stated
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
AC Characteristics
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Rise Time
1
Tr1
20pF load, 0.8 to 2.0V
PCLK & BCLK
-0.91.5ns
Fall Time
1
Tf1
20pF load, 2.0 to 0.8V
PCLK & BCLK
-0.81.4ns
Rise Time
1
Tr2
20pF load, 20% to 80%
PCLK & BCLK
-1.52.5ns
Fall Time
1
Tf2
20pF load, 80% to 20%
PCLK & BCLK
-1.42.4ns
Duty Cycle
1
Dt
20pF load
@ V
OUT = 1.4 V
45 50 55 %
Jitter, One Sigma
1
Tj1s1
PCLK & BCLK Clocks;
Load=20pF,
F
OUT >25 MHz
- 50 150 ps
Jitter, Absolute
1
Tjab1
PCLK & BCLK Clocks;
Load=20pF,
F
OUT
>25 MHz
-250 - 250 ps
Jitter, One Sigma
1
Tj1s2 Fixed CLK; Load=20pF - 1 3 %
Jitter, Absolute
1
Tjab2 Fixed CLK; Load=20pF -5 2 5 %
Input Frequency
1
Fj 12.0 14.318 16.0 MHz
Logic Input
Capacitance
1
CIN Logic input pins - 5 - pF
Crystal Oscillator
Capacitance
1
CINX X1, X2 pins - 18 - pF
Power-on Time
1
ton
From VDD=1.6V to 1st
crossing of 66.5 MHz V
DD
supply ramp < 40 ms
-2.54.5ms
Frequency Settling
Time
1
ts
From 1st crossing of
acquisition to < 1% settling
-2.04.0ms
Clock Skew
Window
1
Tsk1
PCLK to PCLK;
Load=20pF; @1.4V
- 150 250 ps
Clock Skew
Window
1
Tsk2
BCLK to BCLK;
Load=20pF; @1.4V
- 300 500 ps
Clock Skew
Window
1
Tsk3
PCLK to BCLK;
Load=20pF; @1.4V
12.65ns
5
ICS9169-01
Electrical Characteristics at 5.0 V
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
V
DD
= 4.5 - 5.5 V, T
A
= 0 - 70
o
C unless otherwise stated
DC Characteristics
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Input Low Voltage V
IL --0.8V
Input High Voltage V
IH 2.4 - - V
Input Low Current I
IL VIN = 0 V -45 -15 -
µA
Input High Current I
IH VIN = VDD -5.0 - 5.0
µA
Output Low Current
1
IOL
VOL = 0.8 V;
for PCLKs & BCLKs
36.0 62.0 - mA
Output High Current
1
IOH
VOL = 2.0 V;
for PCLKs & BCLKs
- -152 -90.0 mA
Output Low Current
1
IOL VOL = 0.8V; for fixed CLKs 30.0 50.0 - mA
Output High Current
1
IOH VOL=2.0V; for fixed CLKs - -110.0 -65.0 mA
Output Low Voltage
1
VOL
IOL = 20 mA;
for PCLKs & BCLKs
-0.250.4V
Output High Voltage
1
VOH
IOH = -70 mA;
for PCLKs & BCLKs
2.4 4.0 - V
Output Low Voltage
1
VOL IOL = 15mA; for fixed CLKs - 0.2 0.4 V
Output High Voltage
1
VOH IOH=-50mA; for fixed CLKs 2.4 4.7 - V
Supply Current
1
IDD @ 66.5 MHz; all outputs unloaded - 80.0 160.0 mA
6
ICS9169-01
General Layout Precautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
traces.
2) Make all power traces and vias as
wide as possible to lower inductance.
Notes:
1) All clock outputs should have series
terminating resistor. Not shown in
all places to improve readibility of
diagram.
2) 47 ohm / 56pf RC termination should
be used at 50MHz and higher clock
loads.
3) Optional crystal load capacitors are
recommended.
Capacitor Values:
C1, C2 : Crystal load values determined by user
C3 : 100pF ceramic
All unmarked capacitors are 0.01µF ceramic
Connections to VDD:
P1-P3P4-P6P7-P9P10-P10

9169M-01LF

Mfr. #:
Buy 9169M-01LF
Manufacturer:
Description:
IC FREQUENCY GENERATOR 28-SOIC
Lifecycle:
New from this manufacturer.
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