7
ICS9169-01
AC Characteristics
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Rise Time
1
Tr1
20pF load, 0.8 to 2.0V
PCLK & BCLK
-0.550.95ns
Fall Time
1
Tf1
20pF load, 2.0 to 0.8V
PCLK & BCLK
-0.520.90ns
Rise Time
1
Tr2
20pF load, 20% to 80%
PCLK & BCLK
-1.22.1ns
Fall Time
1
Tf2
20pF load, 80% to 20%
PCLK & BCLK
-1.12.0ns
Duty Cycle
1
Dt1 20pF load @ VOUT = 50% of VDD 45 50 55 %
Duty Cycle
1
Dt2 20pF load @ VOUT = 1.4 V 50 55 60 %
Jitter, One Sigma
1
Tj1s1
PCLK & BCLK Clocks; Load=20pF;
R=33
Ω FOUT > 25 MHz
- 50 150 ps
Jitter, Absolute
1
Tjab1
PCLK & BCLK Clocks; Load=20pF;
R=33
Ω FOUT > 25 MHz
-250 - 250 ps
Jitter, One Sigma
1
Tjis2
Fixed CLK; Load=20pF
R=33
Ω
-13%
Jitter, Absolute
1
Tjab2
Fixed CLK; Load=20pF
R=33
Ω
-5 2 5 %
Input Frequency
1
Fi 12.0 14.318 16.0 MHz
Logic Input Capacitance
1
CIN Logic input pins - 5 - pF
Crystal Oscillator
Capacitance
1
CINX X1, X2 pins - 18 - pF
Power-on Time
1
ton
From V=1.6V to 1st crossing of 66.5
MHz V
DD supply ramp < 40 ms
-2.54.5ms
Frequency Settling Time
1
ts
From 1st crossing of acquisition to
< 1% settling
-2.04.0ms
Clock Skew Window
1
Tsk1
PCLK to PCLK;
Load=20pF; @1.4V
- 150 250 ps
Clock Skew Window
1
Tsk2
BCLK to BCLK;
Load=20pF; @1.4V
- 300 500 ps
Clock Skew Window
1
Tsk3
PCLK to BCLK;
Load=20pF; @1.4V
12.65 ns
Electrical Characteristics at 5.0 V
V
DD
= 4.5 - 5.5 V, T
A
= 0 - 70
o
C unless otherwise stated
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
