MAX5156/MAX5157
Power-Down Mode
The MAX5156/MAX5157 feature a software-program-
mable shutdown mode that reduces the typical supply
current to 2µA. The two DACs can be shut down inde-
pendently or simultaneously by using the appropriate
programming word. For instance, enter shutdown mode
(for both DACs) by writing an input control word of
111XXXXXXXXXXXX0 (Table 1). In shutdown mode, the
reference inputs and amplifier outputs become high
impedance, and the serial interface remains active.
Data in the input registers is saved, allowing the
MAX5156/MAX5157 to recall the output state prior to
entering shutdown when returning to normal mode. Exit
shutdown by recalling the previous condition or by
updating the DAC with new information. When returning
to normal operation (exiting shutdown), wait 20µs for
output stabilization.
Serial Interface
The MAX5156/MAX5157 3-wire serial interface is com-
patible with both Microwire (Figure 2) and SPI/QSPI
(Figure 3) serial-interface standards. The 16-bit serial
input word consists of an address bit, two control bits,
12 bits of data (MSB to LSB), and one sub bit as shown
in Figure 4. The address and control bits determine the
response of the MAX5156/MAX5157, as outlined in
Table 1.
Low-Power, Dual, 12-Bit Voltage-Output DACs
with Configurable Outputs
10 ______________________________________________________________________________________
D11................D0
MSB LSB
FUNCTION
A0 C1 C0
0 0 1 12 bits of DAC data Load input register A; DAC register is unchanged.
0 1 1 12 bits of DAC data
Load all DAC registers from the shift register (start up both DACs
with new data).
1 1 0 12 bits of DAC data Load input register B; all DAC registers are updated.
0 1 0 12 bits of DAC data Load input register A; all DAC registers are updated.
1 0 1 12 bits of DAC data Load input register B; DAC register is unchanged.
0 0 0 1 1 0 x xxxxxxxx
Shut down DAC A when PDL = 1.
0 0 0 1 0 1 x xxxxxxxx
Update DAC register B from input register B (start up DAC B with
data previously stored in input register B).
0 0 0 0 0 1 x xxxxxxxx
Update DAC register A from input register A (start up DAC A with
data previously stored in input register A).
1 1 1 xxxxxxxxxxxx
Shut down both DACs if PDL = 1.
1 0 0 xxxxxxxxxxxx
Update both DAC registers from their respective input registers
(start up both DACs with data previously stored in the input
registers).
0 0 0 1 1 1 x xxxxxxxx
Shut down DAC B when PDL = 1.
0 0 0 0 1 0 x xxxxxxxx UPO goes low (default).
0 0 0 0 1 1 x xxxxxxxx UPO goes high.
0 0 0 1 0 0 1 xxxxxxxx Mode 1, DOUT clocked out on SCLK’s rising edge.
0 0 0 1 0 0 0 xxxxxxxx Mode 0, DOUT clocked out on SCLK’s falling edge (default).
0 0 0 0 0 0 x xxxxxxxx No operation (NOP).
Table 1. Serial-Interface Programming Commands
“x” = don’t care
Note: D11, D10, D9, and D8 become control bits when A0, C1, and C0 = 0. S0 is a sub bit, always zero.
S0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16-BIT SERIAL WORD
The MAX5156/MAX5157’s digital inputs are double
buffered, which allows any of the following: loading the
input register(s) without updating the DAC register(s),
updating the DAC register(s) from the input register(s),
or updating the input and DAC registers concurrently.
The address and control bits allow the DACs to act
independently.
Send the 16-bit data as one 16-bit word (QSPI) or two
8-bit packets (SPI, Microwire), with CS low during this
period. The address and control bits determine which
register will be updated, and the state of the registers
when exiting shutdown. The 3-bit address/control
determines the following:
registers to be updated
clock edge on which data is clocked out via the seri-
al data output (DOUT)
state of the user-programmable logic output
configuration of the device after shutdown
The general timing diagram in Figure 5 illustrates how
data is acquired. Driving CS low enables the device to
receive data. Otherwise, the interface control circuitry is
disabled. With CS low, data at DIN is clocked into the
register on the rising edge of SCLK. As CS goes high,
data is latched into the input and/or DAC registers
depending on the address and control bits. The maxi-
mum clock frequency guaranteed for proper operation
is 10MHz. Figure 6 depicts a more detailed timing dia-
gram of the serial interface.
Serial Data Output (DOUT)
DOUT is the internal shift register’s output. It allows for
daisy-chaining and data readback. The MAX5156/
MAX5157 can be programmed to shift data out of
DOUT on SCLK’s falling edge (Mode 0) or rising edge
(Mode 1). Mode 0 provides a lag of 16 clock cycles,
which maintains compatibility with SPI/QSPI and
Microwire interfaces. In Mode 1, the output data lags
15.5 clock cycles. On power-up, the device defaults to
Mode 0.
User-Programmable Logic Output (UPO)
UPO allows an external device to be controlled through
the MAX5156/MAX5157 serial interface (Table 1), there-
by reducing the number of microcontroller I/O pins
required. On power-up, UPO is low.
Power-Down Lockout Input (PDL)
PDL disables software shutdown when low. When in
shutdown, transitioning PDL from high to low wakes up
the part with the output set to the state prior to shut-
down. PDL can also be used to asynchronously wake
up the device.
MAX5156/MAX5157
Low-Power, Dual, 12-Bit Voltage-Output DACs
with Configurable Outputs
______________________________________________________________________________________ 11
SCLK
DIN
CS
SK
SO
I/O
MAX5156
MAX5157
MICROWIRE
PORT
Figure 2. Connections for Microwire
DIN
SCLK
CS
MOSI
SCK
I/O
SPI/QSPI
PORT
SS
V
CC
CPOL = 0, CPHA = 0
MAX5156
MAX5157
Figure 3. Connections for SPI/QSPI
Figure 4. Serial-Data Format
1 Address/2 Control Bits
A0
0
Address Bits
C1, C0
Control Bits
S0
12 Data Bits
D11.......................D0
MSB...DataBits...LSB
Sub
Bit
16 Bits of Serial Data
MSB...................................................................................LSB
MAX5156/MAX5157
Daisy Chaining Devices
Any number of MAX5156/MAX5157s can be daisy
chained by connecting the DOUT pin of one device to the
DIN pin of the following device in the chain (Figure 7).
Since the MAX5156/MAX5157’s DOUT has an internal
active pull-up, the DOUT sink/source capability deter-
mines the time required to discharge/charge a capaci-
tive load. Refer to the digital output V
OH
and V
OL
speci-
fications in the
Electrical Characteristics
.
Figure 8 shows an alternative method of connecting
several MAX5156/MAX5157s. In this configuration, the
data bus is common to all devices; data is not shifted
through a daisy-chain. More I/O lines are required in
this configuration because a dedicated chip-select
input (CS) is required for each IC.
Low-Power, Dual, 12-Bit Voltage-Output DACs
with Configurable Outputs
12 ______________________________________________________________________________________
CS
SCLK
DIN
COMMAND
EXECUTED
9
8
16
1
C1
A0 S0
C0
D11
D10
D9
D8 D5 D4 D3 D2 D1 D0D7 D6
Figure 5. Serial-Interface Timing Diagram
SCLK
DIN
t
CSO
t
CSS
t
CL
t
CH
t
CP
t
CSW
t
CS1
t
CSH
t
DS
t
DH
CS
Figure 6. Detailed Serial-Interface Timing Diagram
TO OTHER
SERIAL DEVICES
MAX5156
MAX5157
DIN
SCLK
CS
MAX5156
MAX5157
MAX5156
MAX5157
DINDOUT DOUT DOUT
SCLK
CS
DIN
SCLK
CS
Figure 7. Daisy Chaining MAX5156/MAX5157s

MAX5156BCEE+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Digital to Analog Converters - DAC 12-Bit 2Ch Precision DAC
Lifecycle:
New from this manufacturer.
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