NBC12430, NBC12430A
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10
Table 11. Frequency Operating Range
VCO Frequency (MHz) Range for a Crystal Frequency (MHz) of:
Output Frequency (MHz) for
F
XTAL
= 16 MHz and for N =
M M[8:0] 10 12 14 16 18 20 B1 B2 B4 B8
160 010100000 400
170 010101010 425
180 010110100 405 450
190 010111110 427.5 475
200 011001000 400 450 500 400 200 100 50
210 011010010 420 472.5 525 420 210 105 52.5
220 011011100 440 495 550 440 220 110 55
230 011100110 402.5 460 517.5 575 460 230 115 57.5
240 011110000 420 480 540 600 480 240 120 60
250 011111010 437.5 500 562.5 625 500 250 125 62.5
260 100000100 455 520 585 650 520 260 130 65
270 100001110 405 472.5 540 607.5 675 540 270 135 67.5
280 100011000 420 490 560 630 700 560 280 140 70
290 100100010 435 507.5 580 652.5 725 580 290 145 72.5
300 100101100 450 525 600 675 750 600 300 150 75
310 100110110 465 542.5 620 697.5 775 620 310 155 77.5
320 101000000 400 480 560 640 720 800 640 320 160 80
330 101001010 412.5 495 577.5 660 742.5 660 330 165 82.5
340 101010100 425 510 595 680 765 680 340 170 85
350 101011110 437.5 525 612.5 700 787.5 700 350 175 87.5
360 101101000 450 540 630 720 720 360 180 90
370 101110010 462.5 555 647.5 740 740 370 185 92.5
380 101111100 475 570 665 760 760 380 190 95
390 110000110 487.5 585 682.5 780 780 390 195 97.5
400 110010000 500 600 700 800 800 400 200 100
410 110011010 512.5 615 717.5
420 110100100 525 630 735
430 110101110 537.5 645 752.5
440 110111000 550 660 770
450 111000010 562.5 675 787.5
460 111001100 575 690
470 111010110 587.5 705
480 111100000 600 720
490 111101010 612.5 735
500 111110100 625 750
510 111111110 637.5 765
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11
Most of the signals available on the TEST output pin are
useful only for performance verification of the device itself.
However, the PLL bypass mode may be of interest at the
board level for functional debug. When T[2:0] is set to 110,
the device is placed in PLL bypass mode. In this mode the
S_CLOCK input is fed directly into the M and N dividers.
The N divider drives the F
OUT
differential pair and the M
counter drives the TEST output pin. In this mode the
S_CLOCK input could be used for low speed board level
functional test or debug. Bypassing the PLL and driving
F
OUT
directly gives the user more control on the test clocks
sent through the clock tree. Figure 7 shows the functional
setup of the PLL bypass mode. Because the S_CLOCK is a
CMOS level the input frequency is limited to 250 MHz or
less. This means the fastest the F
OUT
pin can be toggled via
the S_CLOCK is 250 MHz as the minimum divide ratio of
the N counter is 1. Note that the M counter output on the
TEST output will not be a 50% duty cycle due to the way the
divider is implemented.
Table 12.
T2 T1 T0 TEST (Pin 20)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SHIFT REGISTER OUT
HIGH
FREF
M COUNTER OUT
F
OUT
LOW
PLL BYPASS
F
OUT
4
Figure 5. Parallel Interface Timing Diagram
M[8:0]
N[1:0]
P_LOAD
VALID
t
h
t
s
M, N to P_LOAD
Figure 6. Serial Interface Timing Diagram
S_CLOCK
S_DATA
S_LOAD
Last
Bit
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12
T2 T1 T0 N1 N0 M6 M5 M4 M3 M2 M1 M0
First
Bit
t
s
t
s
t
h
t
h
S_CLOCK to S_LOAD
S_DATA to S_CLOCK
C13 C14
M7M8
Figure 7. Serial Test Clock Block Diagram
FDIV4
MCNT
LOW
F
OUT
MCNT
FREF
HIGH
TEST
MUX
7
0
TEST
F
OUT
(VIA ENABLE GATE)
N
(1, 2, 4, 8)
0
1
PLL 12430
LATCH
Reset
PLOAD
M COUNTER
SLOAD
T0
T1
T2
VCO_CLK
SHIFT
REG
14BIT
DECODE
SDATA
SCLOCK
MCNT
FREF_EXT
T2=T1=1, T0=0: Test Mode
SCLOCK is selected, MCNT is on TEST output, SCLOCK N is on F
OUT
pin.
PLOAD acts as reset for test pin latch. When latch reset, T2 data is shifted out TEST pin.
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12
APPLICATIONS INFORMATION
Using the OnBoard Crystal Oscillator
The NBC12430 and NBC12430A feature a fully
integrated onboard crystal oscillator to minimize system
implementation costs. The oscillator is a series resonant,
multivibrator type design as opposed to the more common
parallel resonant oscillator design. The series resonant
design provides better stability and eliminates the need for
large load capacitors per Figure 8 (do not use crystal load
caps). The oscillator is totally self contained so that the only
external component required is the crystal. As the oscillator
is somewhat sensitive to loading on its inputs, the user is
advised to mount the crystal as close to the device as possible
to avoid any board level parasitics. To facilitate colocation,
surface mount crystals are recommended, but not required.
Because the series resonant design is affected by capacitive
loading on the crystal terminals, loading variation
introduced by crystals from different vendors could be a
potential issue. For crystals with a higher shunt capacitance,
it may be required to place a resistance, optional R
shunt
,
across the terminals to suppress the third harmonic.
Although typically not required, it is a good idea to layout
the PCB with the provision of adding this external resistor.
The resistor value will typically be between 500 W and 1 kW.
Figure 8. Crystal Application
The oscillator circuit is a series resonant circuit and thus,
for optimum performance, a series resonant crystal should
be used. Unfortunately, most crystals are characterized in a
parallel resonant mode. Fortunately, there is no physical
difference between a series resonant and a parallel resonant
crystal. The difference is purely in the way the devices are
characterized. As a result, a parallel resonant crystal can be
used with the device with only a minor error in the desired
frequency. A parallel resonant mode crystal used in a series
resonant circuit will exhibit a frequency of oscillation a few
hundred ppm lower than specified (a few hundred ppm
translates to kHz inaccuracies). In a general computer
application, this level of inaccuracy is immaterial. Table 13
below specifies the performance requirements of the
crystals to be used with the device.
Table 13. Crystal Specifications
Parameter Value
Crystal Cut Fundamental AT Cut
Resonance Series Resonance*
Frequency Tolerance ±75 ppm at 25°C
Frequency/Temperature Stability ±150 ppm 0 to 70°C
Operating Range 0 to 70°C
Shunt Capacitance 57 pF
Equivalent Series Resistance (ESR)
50 to 80 W
Correlation Drive Level
100 mW
Aging 5 ppm/Yr
(First 3 Years)
* See accompanying text for series versus parallel resonant
discussion.
Power Supply Filtering
The NBC12430 and NBC12430A are mixed
analog/digital product and as such, it exhibits some
sensitivities that would not necessarily be seen on a fully
digital product. Analog circuitry is naturally susceptible to
random noise, especially if this noise is seen on the power
supply pins. The NBC12430 and NBC12430A provide
separate power supplies for the digital circuitry (V
CC
) and
the internal PLL (PLL_V
CC
) of the device. The purpose of
this design technique is to try and isolate the high switching
noise of the digital outputs from the relatively sensitive
internal analog phaselocked loop. In a controlled
environment such as an evaluation board, this level of
isolation is sufficient. However, in a digital system
environment where it is more difficult to minimize noise on
the power supplies, a second level of isolation may be
required. The simplest form of isolation is a power supply
filter on the PLL_V
CC
pin for the NBC12430 and
NBC12430A .
Figure 9 illustrates a typical power supply filter scheme.
The NBC12430 and NBC12430A are most susceptible to
noise with spectral content in the 1 KHz to 1 MHz range.
Therefore, the filter should be designed to target this range.
The key parameter that needs to be met in the final filter
design is the DC voltage drop that will be seen between the
V
CC
supply and the PLL_V
CC
pin of the NBC12430 and
NBC12430A . From the data sheet, the PLL_V
CC
current
(the current sourced through the PLL_V
CC
pin) is typically
24 mA (30 mA maximum). Assuming that a minimum of
2.8 V must be maintained on the PLL_V
CC
pin, very little
DC voltage drop can be tolerated when a 3.3 V V
CC
supply
is used. The resistor shown in Figure 9 must have a
resistance of 1015 W to meet the voltage drop criteria. The
RC filter pictured will provide a broadband filter with
approximately 100:1 attenuation for noise whose spectral
content is above 20 kHz. As the noise frequency crosses the

NBC12430FAG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Phase Locked Loops - PLL 3.3V/5V Programmable PLL Clock Generator
Lifecycle:
New from this manufacturer.
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