NBC12430, NBC12430A
http://onsemi.com
13
series resonant point of an individual capacitor, it’s overall
impedance begins to look inductive and thus increases with
increasing frequency. The parallel capacitor combination
shown ensures that a low impedance path to ground exists
for frequencies well above the bandwidth of the PLL.
Figure 9. Power Supply Filter
PLL_V
CC
V
CC
NBC12430
NBC12430A
0.01 mF
22 mF
L=1000 mH
R=15 W
0.01 mF
3.3 V or
5.0 V
R
S
= 1015 W
3.3 V or
5.0 V
A higher level of attenuation can be achieved by replacing
the resistor with an appropriate valued inductor. Figure 9
shows a 1000 mH choke. This value choke will show a
significant impedance at 10 KHz frequencies and above.
Because of the current draw and the voltage that must be
maintained on the PLL_V
CC
pin, a low DC resistance
inductor is required (less than 15 W). Generally, the
resistor/capacitor filter will be cheaper, easier to implement,
and provide an adequate level of supply filtering.
The NBC12430 and NBC12430A provide
subnanosecond output edge rates and therefore a good
power supply bypassing scheme is a must. Figure 10 shows
a representative board layout for the NBC12430 and
NBC12430A . There exists many different potential board
layouts and the one pictured is but one. The important aspect
of the layout in Figure 10 is the low impedance connections
between V
CC
and GND for the bypass capacitors.
Combining good quality general purpose chip capacitors
with good PCB layout techniques will produce effective
capacitor resonances at frequencies adequate to supply the
instantaneous switching current for the device outputs. It is
imperative that low inductance chip capacitors are used. It
is equally important that the board layout not introduce any
of the inductance saved by using the leadless capacitors.
Thin interconnect traces between the capacitor and the
power plane should be avoided and multiple large vias
should be used to tie the capacitors to the buried power
planes. Fat interconnect and large vias will help to minimize
layout induced inductance and thus maximize the series
resonant point of the bypass capacitors.
Figure 10. PCB Board Layout (PLCC28)
C2
1
C3
R1
XTAL
C1 C1
R1 = 1015 W
C1 = 0.01 mF
C2 = 22 mF
C3 = 0.1 mF
= V
CC
= GND
= Via
R
shunt
Opt. R
shunt
= 500 W 1 kW
Note the dotted lines circling the crystal oscillator
connection to the device. The oscillator is a series resonant
circuit and the voltage amplitude across the crystal is
relatively small. It is imperative that no actively switching
signals cross under the crystal as crosstalk energy coupled
to these lines could significantly impact the jitter of the
device. Special attention should be paid to the layout of the
crystal to ensure a stable, jitter free interface between the
crystal and the onboard oscillator. Note the provisions for
placing a resistor across the crystal oscillator terminals as
discussed in the crystal oscillator section of this data sheet.
Although the NBC12430 and NBC12430A have several
design features to minimize the susceptibility to power
supply noise (isolated power and grounds and fully
differential PLL), there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter and bypass schemes
discussed in this section should be adequate to eliminate
power supply noiserelated problems in most designs.
Jitter Performance
Jitter is a common parameter associated with clock
generation and distribution. Clock jitter can be defined as the
deviation in a clock’s output transition from its ideal
position.
CycletoCycle Jitter (shortterm) is the period
variation between two adjacent cycles over a defined
number of observed cycles. The number of cycles observed
is application dependent but the JEDEC specification is
1000 cycles.
NBC12430, NBC12430A
http://onsemi.com
14
Figure 11. CycletoCycle Jitter
T
JITTER(cyclecycle)
= T
1
T
0
T
0
T
1
PeaktoPeak Jitter is the difference between the
highest and lowest acquired value and is represented as the
width of the Gaussian base.
Figure 12. PeaktoPeak Jitter
Time
Typical
Gaussian
Distribution
RMS
or one
Sigma
Jitter
Jitter Amplitude
PeaktoPeak Jitter (8 s)
There are different ways to measure jitter and often they
are confused with one another. The typical method of
measuring jitter is to look at the timing signal with an
oscilloscope and observe the variations in periodtoperiod
or cycletocycle. If the scope is set up to trigger on every
rising or falling edge, set to infinite persistence mode and
allowed to trace sufficient cycles, it is possible to determine
the maximum and minimum periods of the timing signal.
Digital scopes can accumulate a large number of cycles,
create a histogram of the edge placements and record
peaktopeak as well as standard deviations of the jitter.
Care must be taken that the measured edge is the edge
immediately following the trigger edge. These scopes can
also store a finite number of period durations and
postprocessing software can analyze the data to find the
maximum and minimum periods.
Recent hardware and software developments have
resulted in advanced jitter measurement techniques. The
Tektronix TDSseries oscilloscopes have superb jitter
analysis capabilities on noncontiguous clocks with their
histogram and statistics capabilities. The Tektronix
TDSJIT2/3 Jitter Analysis software provides many key
timing parameter measurements and will extend that
capability by making jitter measurements on contiguous
clock and data cycles from singleshot acquisitions.
M1 by Amherst was used as well and both test methods
correlated.
This test process can be correlated to earlier test methods
and is more accurate. All of the jitter data reported on the
NBC12430 and NBC12430A was collected in this manner.
Figure 14 shows the jitter as a function of the output
frequency. The graph shows that for output frequencies from
50 to 800 MHz the jitter falls within the 20 ps
peaktopeak specification. The general trend is that as the
output frequency is increased, the output edge jitter will
decrease.
Figure 13 illustrates the RMS jitter performance of the
NBC12430 and NBC12430A across its specified VCO
frequency range. Note that the jitter is a function of both the
output frequency as well as the VCO frequency. However,
the VCO frequency shows a much stronger dependence. The
data presented has not been compensated for trigger jitter.
LongTerm Period Jitter is the maximum jitter
observed at the end of a period’s edge when compared to the
position of the perfect reference clock’s edge and is specified
by the number of cycles over which the jitter is measured.
The number of cycles used to look for the maximum jitter
varies by application but the JEDEC spec is 10,000 observed
cycles.
The NBC12430 and NBC12430A exhibit long term and
cycletocycle jitter, which rivals that of SAW based
oscillators. This jitter performance comes with the added
flexibility associated with a synthesizer over a fixed
frequency oscillator. The jitter data presented should
provide users with enough information to determine the
effect on their overall timing budget. The jitter performance
meets the needs of most system designs while adding the
flexibility of frequency margining and field upgrades. These
features are not available with a fixed frequency SAW
oscillator.
Figure 13. RMS Jitter vs. VCO Frequency
VCO FREQUENCY (MHz)
400 500 600 700 800
25
20
15
10
5
0
RMS JITTER (ps)
N = 1
N = 8
N = 2
N = 4
Figure 14. RMS Jitter vs. Output Frequency
25
20
15
10
5
0
RMS JITTER (ps)
800700600500400300200100
OUTPUT FREQUENCY (MHz)
NBC12430, NBC12430A
http://onsemi.com
15
t
SETUP
t
HOLD
S_CLOCK
S_DATA
Figure 15. Setup and Hold
t
SETUP
t
HOLD
S_LOAD
S_DATA
Figure 16. Setup and Hold
t
SETUP
t
HOLD
P_
LOAD
M[8:0]
Figure 17. Setup and Hold
t
PERIOD
Pulse Width
F
OUT
F
OUT
Figure 18. Output Duty Cycle
N[1:0]
DCO
tpw
tPERIOD

NBC12430FAG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Phase Locked Loops - PLL 3.3V/5V Programmable PLL Clock Generator
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union