U4256BM
Rev. A5, 06-Oct-00
Preliminary Information
4 (14)
Electrical Characteristics (continued)
Test conditions (unless otherwise specified): V
S
= +8.5 V, T
amb
= +25°C
Parameters Test Conditions / Pins Symbol Min. Typ. Max. Unit
Pulsed current output PD Pin 2
Output current Bit 71, 70 = ‘00’ PD = 2.5 V ± IPD 20 25 30 µA
Output current Bit 71, 70 = ‘001’ 80 100 120 µA
Output current Bit 71, 70 = ‘10’ 400 500 600 µA
Output current Bit 71, 70 = ‘11’ 1600 2000 2400 µA
Leakage current PD = 2.5 V ± IPDL 20 nA
PDO Pin 1
Saturation voltage HIGH
LOW
I = 15 mA V
PDOH
V
PDOL
0.1 0.2
V
S
– 0.5
0.4
V
V
SWO1, SWO2, SWO3, SWO4 (open drain) Pins 7, 8, 9 and 10
Output leakage current
HIGH
V7,8,9,10 = 8.5 V I
SWOH
100 nA
Output voltage LOW I = 1 mA V
SWOL
100 400 mV
DAC1, DAC2 Pins 3 and 4
Output current I
DAC1,
2
± 1 mA
Output voltage V
DAC1,
2
0.3 V
S
– 0.5 V
Gain range (resolution 256 steps) 0.6 2.3
Offset range (resolution 24 steps) –0.6 0.7 V
DAC 3 Pin 5
Output current I
DAC3
± 1 mA
Output voltage (resolution 16 steps) V
DAC3
0.25 6 V
3-Wire Bus Description
12
24-bit command
16-bit command
DATA
CLK
LSB LSBMSB MSBBYTE 1 BYTE 2
ENEN
CLK
DATA
LSB
LSB
MSB
MSB BYTE 3BYTE 2 MSBLSBBYTE 1
EN
e.g., Divider
0
02
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
2
10
2
11
2
2
13
IPD
P–2
1
R–Divider Addr.
P–2
0
P–2
2
Status 0
OSCB
2
14
2
15
DAC3
Figure 3. Pulse diagram
U4256BM
Preliminary Information
Rev. A5, 06-Oct-00 5 (14)
Data Transfer
A
MSB Byte 3 LSB MSB BYTE 2 LSB MSB BYTE 1 LSB
ADDR STATUS 0 DAC3 R – DIVIDER
0 0 IPD OSCB
0 = on,
1 = off
P–2
2
P–2
1
P–2
0
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
B71 B70 B69 B68 B67 B66 B65 B64 B63 B62 B61 B60 B59 B58 B57 B56 B55 B54 B53 B52 B51 B50
B
MSB Byte 3 LSB MSB BYTE 2 LSB MSB BYTE 1 LSB
ADDR STATUS 1 N – DIVIDER
0 1 0
AM=1
FM=0
DAC
SWO4
1=off,
0=on
SWO3
1=off,
0=on
SWO2
1=off,
0=on
SWO1
1=off,
0=on
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
B35 B34 B33 B32 B31 B30 B29 B28 B27 B25 B24 B23 B22 B22 B21 B20 B19 B18 B17 B16 B15 B14
C
MSB BYTE 2 LSB MSB BYTE 1 LSB
ADDR DAC1 OFFSET DAC1 GAIN
0 0 O–2
5
O–2
4
O–2
3
O–2
2
O–2
1
O–2
0
G–2
7
G–2
6
G–2
5
G–2
4
G–2
3
G–2
2
G–2
1
G–2
0
B49 B48 B47 B46 B45 B44 B43 B42 B41 B40 B39 B38 B37 B36
D
MSB BYTE 2 LSB MSB BYTE 1 LSB
ADDR DAC2 OFFSET DAC2 GAIN
0 1 O–2
5
O–2
4
O–2
3
O–2
2
O–2
1
O–2
0
G–2
7
G–2
6
G–2
5
G–2
4
G–2
3
G–2
2
G–2
1
G–2
0
B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
E
MSB BYTE 2 LSB MSB BYTE 1 LSB
ADDR Oscillator tuning function Not used
1 0 8pF 32pF 16pF 8pF 4pF 2pF 1pF 0.5pF X X X X X X
B85 B84 B83 B82 B81 B80 B79 B78 B77 B76 B75 B74 B73 B72
U4256BM
Rev. A5, 06-Oct-00
Preliminary Information
6 (14)
Timing Information
Parameters Test Conditions / Pins Symbol Min. Typ. Max. Unit
3-wire bus, ENABLE, DATA, CLOCK Pins 16, 17, 18
Input voltage HIGH
LOW
V
BUSH
V
BUSL
2.0
1.0
V
V
Clock frequency 1.0 MHz
Period of CLK HIGH
LOW
t
H
t
L
250
250
ns
ns
Rise time EN, DATA, CLK t
r
400 ns
Fall time EN, DATA, CLK t
f
100 ns
Set-up time t
s
100 ns
Hold time EN t
HEN
250 ns
Hold time DATA t
HDA
0 ns
Bus Timing
t
R
t
F
t
R
t
S
t
F
t
HEN
t
R
t
S
t
HDA
t
F
t
H t
L
Enable
Data
Clock
Figure 4. Bus timing

U4256BM-NFS

Mfr. #:
Manufacturer:
Description:
IC SYNTHESIZER FREQ RADIO 20SSOP
Lifecycle:
New from this manufacturer.
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