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U4256BM-NFS

P1-P3P4-P6P7-P9P10-P12P13-P14
U4256BM
Preliminary Information
Rev. A5, 06-Oct-00 7 (14)
Bus Control
The charge-pump current can be choosen by setting the
Bits 71 and 70 as following:
IPD (µA) B71 B70
25 0 0
100 0 1
500 1 0
2000 1 1
The oscillator buffer output can be switched by the OSCB
Bit as following (Bit 69):
MX2LO AC Voltage B69
ON 0
OFF 1
The DAC3 output voltage can be controlled by the
Bits P-2
0
to P-2
2
(Bits 66 to 68) as following:
DAC3 Offset Approx. B68 B67 B66
0.5 V 0 0 0
1.1 V 0 0 1
1.8 V 0 1 0
2.4 V 0 1 1
3.1 V 1 0 0
3.7 V 1 0 1
4.4 V 1 1 0
5.0 V 1 1 1
The switching output SWO1 to SWO4 can be controlled
as following (Bits 30 to 33):
Switch Output B29 + X
SWOx = ON
(switch to GND)
0
SWOx = OFF 1
The DAC mode can be controlled by setting the Bit 34 as
following:
DAC Mode B34
FM 0
AM 1
The gains of DAC1 and DAC2 have a range of
0.7 x V(PDO) to 2.15 x V(PDO). V(PDO) is the PLL
tuning voltage output. This range is divided into 256
steps. So one step is approximately
(2.15–0.7)/256 = 5.664 m. The gain can be controlled by
the Bits 36 to 43 (G–2
0
to G–2
7
) as following:
Gain DAC1
Approx.
B43 B42 B41 B40 B39 B38 B37 B36
Gain DAC2
Approx.
B7 B6 B5 B4 B3 B2 B1 B0
0.7 0 0 0 0 0 0 0 0
0.70566 0 0 0 0 0 0 0 1
0.71133 0 0 0 0 0 0 1 0
0.71699 0 0 0 0 0 0 1 1
... ... ... ... ... ... ... ... ...
1.00019 0 0 1 1 0 1 0 1
... ... ... ... ... ... ... ... ...
2.1386 1 1 1 1 1 1 0 1
2.14434 1 1 1 1 1 1 1 0
2.15 1 1 1 1 1 1 1 1
The offset of DAC1 has a range of 0.5 V to –0.6 V. This
range is divided into 64 steps. So one step is approxi-
mately 1.1V/63 = 17.2 m. The offset can be controlled by
the Bits 44 to 49 (O–2
0
to O–2
5
) as following:
Offset DAC1
Approx. [V]
B49 B48 B47 B46 B45 B44
Offset DAC2
Approx. [V]
B13 B12 B11 B10 B9 B8
0.5 0 0 0 0 0 0
0.4828 0 0 0 0 0 1
0.4656 0 0 0 0 1 0
0.4484 0 0 0 0 1 1
... ... ... ... ... ... ...
–0.0156 0 1 1 1 1 0
... ... ... ... ... ... ...
0.5656 1 1 1 1 0 1
–0.5828 1 1 1 1 1 0
–0.6 1 1 1 1 1 1
The tuning capacity for the crystal oscillator has a range
of 0.5 pF to 71.5 pF. The values are coded binary. The
tuning can be controlled by the Bits 78 to 85 as following:
B85=0
pF
B85=1
pF
B84 B83 B82 B81 B80 B79 B78
0 8.0 1 1 1 1 1 1 1
0.5 8.5 1 1 1 1 1 1 0
1.0 9.0 1 1 1 1 1 0 1
1.5 19.5 1 1 1 1 1 0 0
... ... ... ... ... ... ... ... ...
63.0 71.0 0 0 0 0 0 0 0
63.5 71.5 0 0 0 0 0 0 0
U4256BM
Rev. A5, 06-Oct-00
Preliminary Information
8 (14)
The gain of DAC2 has a range of 0.7 x V(PDO) to
2.15 x V(PDO). V(PDO) is the PLL tuning voltage
output. This range is divided into 256 steps. So one step
is approximately (2.15–0.7)/256 = 5.664 m. The gain can
be controlled by the bits 0 to 7 (G–2
0
to G–2
7
) as
following:
Gain
DAC2
Approx.
B7 B6 B5 B4 B3 B2 B1 B0
0.7 0 0 0 0 0 0 0 0
0.70566 0 0 0 0 0 0 0 1
0.71133 0 0 0 0 0 0 1 0
0.71699 0 0 0 0 0 0 1 1
... ... ... ... ... ... ... ... ...
1.00019 0 0 1 1 0 1 0 1
... ... ... ... ... ... ... ... ...
2.1386 1 1 1 1 1 1 0 1
2.14434 1 1 1 1 1 1 1 0
2.15 m 1 1 1 1 1 1 1 1
The offset of DAC2 has a range of 0.5 to –0.6. This range
is divided into 64 steps. So one step is approximately
1.1V/63 = 17.2 m. The offset can be controlled by the
Bits 8 to 13 (O–2
0
to O–2
5
) as following:
Offset DAC2
Approx.
B13 B12 B11 B10 B9 B8
0.5 0 0 0 0 0 0
0.4828 0 0 0 0 0 1
0.4656 0 0 0 0 1 0
0.4484 0 0 0 0 1 1
... ... ... ... ... ... ...
–0.0156 0 1 1 1 1 0
... ... ... ... ... ... ...
0.5656 1 1 1 1 0 1
–0.5828 1 1 1 1 1 0
–0.6 1 1 1 1 1 1
Input / Output Interface Circuits
PDO
PDO is the loop amplifier output of the PLL. The bipolar
output stage is a rail-to-rail amplifier.
PD
PD is the current charge pump output of the PLL. The
current can be controlled by setting the Bits. The loop
filter has to be designed corresponding to the choosen
pump current and the internal reference frequency. A
recommendation can be found in the application circuit.
V5
PD
PDO
C
Figure 5.
U4256BM
Preliminary Information
Rev. A5, 06-Oct-00 9 (14)
FMOSCIN
FMOSCIN is the preamplifier input for the FM oscillator signal.
FMOSCIN
V
S
Figure 6.
MX2LO
MX2LO is the buffered output of the crystal oscillator.
This signal can be used as a reference frequency for
U4255BM.
V5
V5
OSCIN
MX2LO
Figure 7.
DAC 1, 2 and 3
DAC 1 to 3 are the outputs for automatic tuner alignment.
VS
DAC1
Figure 8.
EN, DATA, CLK
All functions can be controlled via a 3-wire bus consisting
of ENABLE, DATA and CLOCK. The bus is designed for
microcontrollers which operate with 3 V supply voltage.
Details of the data transfer protocol are shown in the table
‘Data Transfer’.
V
S
EN
DATA
CLK
Figure 9.
SWO1, 2, 3 and 4
All switching outputs are ‘open drain’ and can be set and
reset by software control. Details are described in the data
transfer protocol.
SWO1
SWO2
SWO3
SWO4
I
Figure 10.
P1-P3P4-P6P7-P9P10-P12P13-P14

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