QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 997
10/12 BIT 250, 210 AND 170 MSPS ADC
4
POWER
If a DC890B is used to acquire data from the DC997,
the DC890B should be connected to a USB port and
provided an external 6V, 1Amp power supply. The
DC890B will not enable LVDS mode without externally
applied power present. Apply +3.3V across the pins
marked “+3.3V” and “GND” on the DC997. The DC997
demonstration circuit requires up to 500 mA depending
on the sampling rate and the A/D converter supplied.
While the DC890B data collection board is initially pow-
ered by the USB cable, it requires an external power
supply of 6V on the 2.1mm power jack or the adjacent
turrets (+) and (-) before the DC890B will enable LVDS
mode.
ENCODE CLOCK
NOTE: THIS IS NOT A LOGIC LEVEL INPUT
. Apply an
encode clock to the SMA connector on the DC997
demonstration circuit board marked “ENCODE CLK”.
Refer to Table 2 for recommended level, impedance and
coupling. For the best noise performance (SNR AND
SFDR), the ENCODE CLK must be driven with a very
low jitter source. When using a sinusoidal generator,
the amplitude should be large, up to 2.5V
P-P
. Using
bandpass filters on the ENCODE CLK and the Analog
input [AIN] will improve the noise performance by re-
ducing the wideband noise power of the signals. Data
sheet FFT plots are taken with 10 pole LC filters made
by TTE (Los Angeles, CA) to suppress signal generator
harmonics, non-harmonically related spurs and broad
band noise. The very high sampling bandwidth of the
LTC2242 family of parts will fold multiple Nyquist
bands of noise (if present) down to base band raising
the noise floor.
[The LTC2242 family of ADCs provides a flexible En-
code Clock interface capable of accommodating both
single ended and differential sources from LVDS or si-
nusoidal inputs. See the LTC2242 data sheet for other
Encode Clock drive options.]
ANALOG INPUT NETWORK
The input transformer and the RC network on the ana-
log inputs are optimized for 10 to 250MHz. These
components must be optimized for higher or lower in-
put frequencies. Consult the LTC2242 data sheet for
other frequency ranges.
Apply the analog input signal of interest to the SMA
connector on the DC997 demonstration circuit board
marked “AIN”. This input is capacitive coupled to the
input of a MaCom ETC1-1-13 balun or a flux coupled
ETC1-1T transformer. (See Schematic)
DIGITAL OUTPUTS
The LVDS conversion clock output is available on pins
[50, 52] of J2. The LVDS data samples are available on
Pins [8-46, 56-82] for 12 BITS or [8-46, 56-
70] for 10 BITS as LVDS pairs isolated by a ground pin
between each set. The data samples can be collected
via a logic analyzer, cabled to a development system
through a SHORT 100 pin ribbon cable (available from
Samtec - HSC8 series of high speed connectors) or
directly via a DC890B FastDAACS data collection sys-
tem.
SOFTWARE
The DC890B is controlled by the
PScope System Soft-
ware
provided or downloaded from the Linear Technol-
ogy website at http://www.linear.com/software/. If a
DC890B was provided, follow the DC890 Quick Start
Guide and the instructions below.
To start the data collection software if “
PScope.exe
”, is
installed (by default) in \Program Files\LTC\PScope\,
double click the PScope Icon or bring up the run win-
dow under the start menu and browse to the PScope
directory and select PScope.
If the DC997 demonstration circuit is properly con-
nected to the DC890, PSCOPE should automatically
detect the DC997, and configure itself accordingly. If
necessary the procedure below explains how to manu-
ally configure PSCOPE.
Under the “Configure” menu, go to “ADC Configura-
tion....” Check the “Config Manually” box and use the
following configuration options, see Figure 2:
Bits: 12 (or 10 for 10 bits parts)
