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Functional Description TSM006
7/13
Automatic burst mode
Burst mode is used during light load condition to
reduce the number of MOS switching, and thus
reducing overall power dissipation. Light load
condition is detected when COMP voltage is low.
When COMP voltage is lower than a threshold
V
BL1
set by the external BL pin, the device output
is forced to off state, providing minimum duty
cycle and pulse skipping.
The burst status is available on the BS pin to put
other devices in standby mode when in light load
condition.
When COMP voltage (Vcomp) is higher than
V
BL2
, the device operates in normal mode.
Current is limited to (Vcomp-2*Vbe)/3 / Rshunt
(Rshunt is the shunt resistor used to measure the
primary current, Vbe is the forward voltage of a
diode, and 3 is the R/2R network attenuation).
Maximum current is 1V/Rshunt. When Vcomp
becomes lower than V
BL
, device enters burst
mode, PWM is stopped while Comp voltage is
lower than V
BL
. As PWM is stopped, no more
energy is transferred to the secondary side,
output voltage is decreasing, and Vcomp (which is
an image of the error comparator) tends to
increase. As soon as Vcomp becomes just higher
than V
BL
, PWM operation can resume for some
cycles, so current in burst mode is limited to (V
BL
-
2*Vbe)/3 / Rshunt.
OverCurrent detection and Hiccup mode
Overcurrent is detected when voltage at the CS
pin is greater than Vz2=1.2V. To avoid false
triggering, the overcurrent detection is delayed in
the same way than the normal pulse by pulse
current limitation.
When overcurrent is detected, the device enters
the hiccup mode. Output is switched off
immediately and the soft start capacitor is
discharged slowly. When the SS pin voltage goes
below 0.5V, normal soft start is started. If the
overcurrent is no more present, device operation
is resumed normally, otherwise, overcurrent is
detected again and the cycle is repeated until the
overcurrent situation disappears.
Duty cycle of the hiccup mode is set by the ratio of
SS pin discharge and charge currents: 10% typ.
With a typical capacitor Css=100nF, soft start
delay is about 40ms and hiccup off-time is 400ms.
Latched disable function
Disable mode is entered when the DIS pin voltage
is driven above 2.5V. Disable state is latched and
can only be exit by driving the Vin power supply
voltage under the UVLO level.
Thermal shutdown
The device operation is shut down when the
internal temperature exceed 130°C. Hysteresis
provides stable working and shutdown states.
Obsolete Product(s) - Obsolete Product(s)
TSM006 Functional Description
8/13
Fig. 1: Detailed Internal Schematic
Pgnd
Vin
Out
Comp
Ss
Rt/Ct
Vref
Cs
Vref
Vin
Vref_Status
Standby
Rex
Rb
Vz2=1.2V
11k
Vref
Frequency
0.5V
1.4V-3.0V
2.5V
Rex
Bs
Vbl1
Vref
FM
Dis
Comp_Dis
R
S
Q
!Q
Disable_Latch
UVLO
Cref
Comp_0cp R
S
Q
!Q
Hiccup_Latch
Icomp
600µA
Thermal
Shutdown
Comp_burst
Comp_Cs
VF VF
2R
R
1V
Ct
Comp_Osc
Idct1
300µA
R
S
Q
!Q
Cs_Latch
R
S
Q
!Q
Start up_Latch
Iiss
10µA
Css
Idss1
1µA
Idss2
1mA
Comp_ss
Comp_Hiccup
28V
Comp_burst
Vbl2
R
S
Q
!Q
Bs_latch
Current source
BL
Cslope
14
4
8
1
6
Rt
Vref
2
CFm
Modulation
5
12
13
7
11
10
9
LEB
Idct2
1mA
3
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Timing Diagram TSM006
9/13
5 Timing Diagram
Timing for PWM function
Timing at Vref rise up and shut down
RT/CT
COMP
CS
(COMP-2VF)/3
OUT
Driving by maximum duty cycle
Driving by PWM No output
Vin
UVLO
Vref
VrefStatus
RT/CT
Startup
4.7V
12V
8.4V
2V
VH
VL
OUT

TSM006IDT

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
IC REG CTRLR PWM CM 14-SOIC
Lifecycle:
New from this manufacturer.
Delivery:
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