ADUM4150BRIZ Datasheet ADUM4150BRIZ, ADUM4150ARIZ-RL, ADUM4150BRIZ-RL | P10-P12

Data Sheet ADuM4150

Rev. B | Page 9 of 21

ELECTRICAL CHARACTERISTICS—MIXED 3.3 V/5 V OPERATION

All typical specifications are at T

= 25°C, V

DD1

= 3.3 V and V

DD2

= 5 V. Minimum and maximum specifications apply over the entire

recommended operation range: 3.0 V ≤ V

DD1

≤ 3.6 V, 4.5 V ≤ V

DD2

≤ 5.5 V, and −40°C ≤ T

≤ +125°C, unless otherwise noted. Switching

specifications are tested with C

= 15 pF and CMOS signal levels, unless otherwise noted.

Table 8. Switching Specifications

Parameter Symbol

A Grade B Grade

Unit Test Conditions/Comments Min Typ Max Min Typ Max

MCLK, MO, SO

SPI Clock Rate SPI

MCLK

9.2 15.6 MHz

Data Rate Fast (MO, SO) DR

FAS T

40 40 Mbps Within PWD limit

Propagation Delay t

PHL

, t

PLH

27 16 ns 50% input to 50% output

Pulse Width PW 12.5 12.5 ns Within PWD limit

Pulse Width Distortion PWD 2 2 ns |t

PLH

− t

PHL

Codirectional Channel Matching

PSKCD

3 3 ns

Jitter, High Speed

MSS

Data Rate Fast DR

FAS T

40 40 Mbps Within PWD limit

Propagation Delay t

PHL

, t

PLH

26 26 ns 50% input to 50% output

Pulse Width PW 12.5 12.5 ns Within PWD limit

Pulse Width Distortion PWD 3 3 ns |t

PLH

− t

PHL

Setup Time

MSS

SETUP

1.5 10 ns

Jitter, High Speed J

1 1 ns

DCLK

Data Rate 40 40 MHz

Propagation Delay t

PHL

, t

PLH

60 40 ns t

PMCLK

+ t

PSO

+ 3 ns

Pulse Width Distortion PWD 3 3 ns |t

PLH

− t

PHL

Pulse Width PW 12 12 ns Within PWD limit

Clock Delay Error DCLK

ERR

2 7 13 2 6.8 11 ns t

PDCLK

− (t

PMCLK

+ t

PSO

)

Jitter J

DCLK

1 1 ns

, V

Data Rate Slow DR

SLOW

250 250 kbps Within PWD limit

Propagation Delay t

PHL

, t

PLH

0.1 2.6 0.1 2.6 µs 50% input to 50% output

Pulse Width PW 4 4 µs Within PWD limit

Jitter, Low Speed J

2.5 2.5 µs

Minimum Input Skew

VIx SKEW

10 10 ns

Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.

The

MSS

signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that

MSS

reaches the output

ahead of another fast signal, set up

MSS

prior to the competing signal by different times depending on speed grade.

PMCLK

is the propagation delay of the MCLK signal from Side 1 to Side 2. t

PSO

is the propagation delay of the SO signal from Side 2 to Side 1. t

PDCLK

is the difference

between the DCLK signal and the round trip propagation delay.

= V

or V

An internal asynchronous clock, not available to users, samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the

leading pulse must be at least 1 t

VIx SKEW

time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.

ADuM4150 Data Sheet

Rev. B | Page 10 of 21

Table 9. For All Grades

1, 2, 3

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

SUPPLY CURRENT

1 MHz, A Grade and B Grade I

DD1

3.5 6 mA C

= 0 pF, DR

FAS T

= 1 MHz,

SLOW

= 0 MHz

DD2

6.8 11 mA C

= 0 pF, DR

FAS T

= 1 MHz,

SLOW

= 0 MHz

17 MHz, B Grade I

DD1

12.5 20 mA C

= 0 pF, DR

FAS T

= 17 MHz,

SLOW

= 0 MHz

DD2

14 21 mA C

= 0 pF, DR

FAS T

= 17 MHz,

SLOW

= 0 MHz

DC SPECIFICATIONS

MCLK,

MSS

, MO, SO, V

, V

Input Threshold

Logic High V

0.7 × V

DDx

Logic Low V

0.3 × V

DDx

Input Hysteresis V

IHYST

500 mV

Input Current per Channel I

−1 +0.01 +1 µA 0 V ≤ V

INPUT

≤ V

DDx

SCLK,

SSS

, MI, SI, V

, V

, DCLK

Output Voltages

Logic High V

DDx

− 0.1 5.0 V I

OUTPUT

= −20 µA, V

INPUT

= V

DDx

− 0.4 4.8 V I

OUTPUT

= −4 mA, V

INPUT

= V

Logic Low V

0.0 0.1 V I

OUTPUT

= 20 µA, V

INPUT

= V

0.2 0.4 V I

OUTPUT

= 4 mA, V

INPUT

= V

DD1

, V

DD2

Undervoltage Lockout UVLO 2.6 V

Supply Current for All Low Speed Channels

Quiescent Side 1 Current I

DD1(Q)

2.9 mA

Quiescent Side 2 Current I

DD2(Q)

6.1 mA

AC SPECIFICATIONS

Output Rise/Fall Time t

2.5 ns 10% to 90%

Common-Mode Transient Immunity

|CM| 25 35 kV/µs V

INPUT

= V

DDx

, V

= 1000 V,

transient magnitude = 800 V

DDx

= V

DD1

or V

DD2

INPUT

is the input voltage of any of the MCLK,

MSS

, MO, SO, V

, or V

pins.

OUTPUT

is the output current of any of the SCLK, DCLK,

SSS

, MI, SI, V

, or V

pins.

|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the V

and V

limits. The common-mode

voltage slew rates apply to both rising and falling common-mode voltage edges.

Data Sheet ADuM4150

Rev. B | Page 11 of 21

PACKAGE CHARACTERISTICS

Table 10.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

Resistance (Input to Output)

I-O

Capacitance (Input to Output)

I-O

1.0 pF f = 1 MHz

Input Capacitance

4.0 pF

IC Junction-to-Ambient Thermal Resistance θ

46 °C/W Thermocouple located at center of package underside

The device is considered a 2-terminal device: Pin 1 through Pin 10 are shorted together, and Pin 11 through Pin 20 are shorted together.

Input capacitance is from any input data pin to ground.

REGULATORY INFORMATION

The ADuM4150 is approved by the organizations listed in Table 11. See Table 16 and the Insulation Lifetime section for recommended

maximum working voltages for specific cross-isolation waveforms and insulation levels.

Table 11.

UL CSA VDE

Recognized Under UL 1577 Component

Recognition Program

Approved under CSA Component Acceptance

Notice 5A

Certified according to DIN V VDE V 0884-10

(VDE V 0884-10):2006-12

5000 V rms Single Protection Basic insulation per CSA 60950-1-07+A1+A2

and IEC 60950-12nd Ed+A1+A2., 800 V rms

(1131 V peak) maximum working voltage

Reinforced insulation, 849 V peak

Reinforced Insulation per CSA 60950-1-

07+A1+A2 and IEC 60950-1 2

Ed.+A1+A2,

400 V rms (565 V peak) maximum working

voltage

Reinforced insulation (2MOPP) per IEC 60601-1

Ed.3.1, 250 V rms (353 V peak) maximum

working

File E214100 File 205078 File 2471900-4880-0001

In accordance with UL 1577, each model is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 10 µA).

In accordance with DIN V VDE V 0884-10, each model is proof tested by applying an insulation test voltage ≥ 1590 V peak for 1 second (partial discharge detection limit = 5 pC).

The asterisk (*) marked on the component designates DIN V VDE V 0884-10

approval.

Use at working voltages above 400 V

RMS

shortens lifetime of the isolator significantly. See Table 16 for recommended maximum working voltages under ac and dc conditions.

INSULATION AND SAFETY RELATED SPECIFICATIONS

Table 12.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 5000 V rms 1-minute duration

Minimum External Air Gap (Clearance) L(I01) 8.3 mm min Measured from input terminals to output terminals,

shortest distance through air

Minimum External Tracking (Creepage) L(I02) 8.3 mm min Measured from input terminals to output terminals,

shortest distance path along body

Minimum Internal Gap (Internal Clearance) 0.017 mm min Insulation distance through insulation

Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1

Material Group

Material Group (DIN VDE 0110, 1/89, Table 1)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

ADUM4150BRIZ

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ADUM4150BRIZ

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