LTC4098/LTC4098-1
23
40981fc
is used in the compensation of the switching regulator. At
least 10μF with low ESR are required on V
OUT
. Additional
capacitance will improve load transient performance
and stability.
Multilayer ceramic chip capacitors typically have excep-
tional ESR performance. MLCCs combined with a tight
board layout and an unbroken ground plane will yield very
good performance and low EMI emissions.
There are several types of ceramic capacitors avail-
able each having considerably different characteristics.
For example, X7R ceramic capacitors have the best voltage
and temperature stability. X5R ceramic capacitors have
apparently higher packing density but poorer performance
over their rated voltage and temperature ranges. Y5V
ceramic capacitors have the highest packing density,
but must be used with caution, because of their extreme
nonlinear characteristic of capacitance versus voltage. The
actual in-circuit capacitance of a ceramic capacitor should
be measured with a small AC signal and DC bias as is
expected in-circuit. Many vendors specify the capacitance
versus voltage with a 1V
RMS
AC test signal and, as a result,
over state the capacitance that the capacitor will present
in the application. Using similar operating conditions as
the application, the user must measure or request from
the vendor the actual capacitance to determine if the
selected capacitor meets the minimum capacitance that
the application requires.
Overprogramming the Battery Charger
The USB high power specification allows for up to 2.5W
to be drawn from the USB port. The switching regulator
transforms the voltage at V
BUS
to just above the voltage
at BAT with high efficiency, while limiting power to less
than the amount programmed at CLPROG. The charger
should be programmed (with the PROG pin) to deliver the
maximum safe charging current without regard to the USB
specifications. If there is insufficient current available to
charge the battery at the programmed rate, it will reduce
charge current until the system load on V
OUT
is satisfied
and the V
BUS
current limit is satisfied. Programming the
charger for more current than is available will not cause
the average input current limit to be violated. It will merely
allow the battery charger to make use of all available
power to charge the battery as quickly as possible, and
with minimal power dissipation within the charger.
Overvoltage Protection
It is possible to protect both V
BUS
and WALL from over-
voltage damage with several additional components, as
shown in Figure 7. Schottky diodes D1 and D2 pass the
larger of V1 and V2 to R1 and OVSENS. If either V1 or V2
exceeds 6V plus V
F(SCHOTTKY)
, OVGATE will be pulled to
GND and both the WALL and USB inputs will be protected.
Each input is protected up to the drain-source breakdown,
BVDSS, of MN1 and MN2. R1 must also be rated for the
power dissipated during maximum overvoltage. See the
Operations section for an explanation of this calculation.
Table 4 shows some N-channel MOSFETs that may be
suitable for overvoltage protection.
Table 4. Recommended OVP FETs
N-CHANNEL
MOSFET BVDSS R
ON
PACKAGE
Si2302ADS 20V
70mΩ
SOT-23
IRLML2502 20V
35mΩ
SOT-23
Si1472DH 30V
65mΩ
SC70-6
NTLJS4114N 30V
20mΩ 2mm × 2mm
DFN
FDN372S 30V
45mΩ
SOT-23
R1
C1
D1
V1
V2
D2
MN1
MN2
40981 F07
WALL
OVSENS
OVGATE
LTC4098/
LTC4098-1
V
BUS
Figure 7. Dual Input Overvoltage Protection
APPLICATIONS INFORMATION
