AD7291-EP Enhanced Product
Rev. 0 | Page 6 of 8
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
14
13
12
1
3
4
SD
A
15
SC
L
AS1
ALERT
1
1
AS0
V
IN3
V
IN5
2
V
IN4
V
IN6
5
V
IN7
7
V
REF
6
GND1
8
D
CAP
9
GND
10
V
DD
19
V
IN1
20
V
IN2
18
V
IN0
17
PD/RST
16
V
DRIVE
15915-002
NOTES
1. THE EXPOSED METAL PADDLE ON THE BOTTOM
OF THE LFCSP PACKAGE SHOULD BE SOLDERED
TO PCB GROUND FOR PROPER HEAT DISSIPATION
AND PERFORMANCE.
TOP VIEW
(Not to Scale)
AD7291-EP
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 to 5,
18 to 20
V
IN3
, V
IN4
,
V
IN5
, V
IN6
,
V
IN7
, V
IN0
,
V
IN1
, V
IN2
Analog Inputs. The AD7291-EP has eight single-ended analog inputs that are multiplexed into the on-chip track-
and-hold amplifier. Each input channel can accept analog inputs from 0 V to 2.5 V. Any unused input channels
must be connected to GND1 to avoid noise pickup.
Ground. Ground reference point for the internal reference circuitry on the AD7291-EP. All analog input signals and
the external reference signals must be referred to this GND1 voltage. The GND1 pin must be connected to the
ground plane of a system. All ground pins must ideally be at the same potential and must not be more than 0.3 V
apart, even on a transient basis. The V
REF
pin must be decoupled to this ground pin via a 10 μF decoupling capacitor.
7 V
REF
Internal Reference/External Reference Supply. The nominal internal reference voltage of 2.5 V appears at this pin.
Provided the output is buffered, the on-
chip reference can be taken from this pin and applied externally to the rest
of a system. Decoupling capacitors must be connected to this pin to decouple the reference buffer. For best
performance, it is recommended to use a 10 μF decoupling capacitor on this pin to GND1. The internal reference
can be disabled and an external reference supplied to this pin if required. The input voltage range for the external
reference is 2.0 V to 2.5 V.
8 D
CAP
Decoupling Capacitor Pin. Decoupling capacitors (1 μF recommended) are connected to this pin to decouple the
internal low dropout regulator (LDO).
9 GND Ground. Ground reference point for all analog and digital circuitry on the AD7291-EP. The GND pin must be con-
nected to the ground plane of the system. All ground pins must ideally be at the same potential and must not be
more than 0.3 V apart, even on a transient basis. Both D
CAP
and V
DD
pins must be decoupled to this GND pin.
10 V
DD
Supply Voltage, 2.8 V to 3.6 V. This supply must be decoupled to GND with 10 μF and 100 nF decoupling capacitors.
11, 13 AS0, AS1 Logic Inputs. Together, the logic state of these two inputs selects a unique I
2
C address for the AD7291-EP. See the
AD7291 data sheet for details. The device address depends on the voltage applied to these pins.
12 ALERT Digital Output. This pin acts as an out-of-range indicator and, if enabled, becomes active when the conversion
result violates the DATA
HIGH
or DATA
LOW
register values. See the AD7291 data sheet for further details.
14 SDA Digital Input/Output. Serial bus bidirectional data. This open-drain output requires a pull-up resistor. The output
coding is straight binary for the voltage channels and twos complement for the temperature sensor result.
15 SCL Digital Inputs. Serial I
2
C Bus Clock. This input requires a pull-up resistor. The data transfer rate in I
2
C mode is
compatible with both 100 kHz and 400 kHz operating modes.
16 V
DRIVE
Logic Power Supply Input. The voltage supplied at this pin determines the voltage at which the interface operates.
This pin must be decoupled to GND. The voltage range on this pin is 1.65 V to 3.6 V and can be less than the
voltage at V
DD
but must never exceed it by more than 0.3 V.
17
PD
/
RST
Power-Down Pin. This pin places the device into a full power-down mode and enables power conservation when
operation is not required. This pin can be used to reset the device by toggling the pin low for a minimum of 1 ns and a
maximum of 100 ns. If the maximum time is exceeded, the device enters power-down mode. When placing the device
in full power-down mode, the analog inputs must be returned to 0 V.
EPAD EPAD Exposed Pad. The exposed metal paddle on the bottom of the LFCSP package must be soldered to PCB ground for
proper functionality and heat dissipation.
