AD7291-EP Enhanced Product
Rev. 0 | Page 8 of 8
OUTLINE DIMENSIONS
0.50
BSC
0.50
0.40
0.30
0.30
0.25
0.18
COMPLIANT
T
O
JEDEC STANDARDS MO-220-WGGD-11.
4.10
4.00 SQ
3.90
0.80
0.75
0.70
0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
COPLANARITY
0.08
PIN 1
INDICA
T
OR
2.75
2.60 SQ
2.35
1
20
6
10
11
15
16
5
BOT
TOM VIEW
T
OP
VIEW
SIDE VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
02-21-2017-B
EXPOSED
PAD
PKG-005089
SEA
TING
PLANE
PIN 1
INDIC
A
T
OR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
Figure 5. 20-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-20-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range Package Description Package Option
AD7291TCPZ-EP −55°C to +125°C 20-Lead Lead Frame Chip Scale Package [LFCSP] CP-20-8
AD7291TCPZ-EP-RL7 −55°C to +125°C 20-Lead Lead Frame Chip Scale Package [LFCSP] CP-20-8
1
Z = RoHS Compliant Part.
I
2
C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15915-0-7/17(0)
