Document #: 38-08052 Rev. *H Page 11 of 15
HS/FS Interface Timing - 30 MHz
Figure 4. 30 MHz Timing Interface Timing Constraints
Figure 5. Tristate Mode Timing Constraints
Table 5. Tristate Mode Timing Constraints Parameters
Table 4. 30 MHz Timing Interface Timing Constraints Parameters
Parameter Description Min Typ Max Unit Notes
T
CSU_MIN
Minimum setup time for TXValid 16 ns
T
CH_MIN
Minimum hold time for TXValid 1 ns
T
DSU_MIN
Minimum setup time for Data (Transmit direction) 16 ns
T
DH_MIN
Minimum hold time for Data (Transmit direction) 1 ns
T
CCO
Clock to Control Out time for TXReady, RXValid,
RXActive and RXError
120ns
T
CDO
Clock to Data out time (Receive direction) 1 20 ns
T
VSU_MIN
Minimum setup time for ValidH (transmit Direction) 16 ns
T
VH_MIN
Minimum hold time for ValidH (Transmit direction) 1 ns
T
CVO
Clock to ValidH out time (Receive direction) 1 20 ns
Parameter Description Min Typ Max Unit Notes
T
tssu
Minimum setup time for Tristate 0 ns
T
tspd
Propagation Delay for Tristate mode 50 ns
TCSU_MIN
TCH_MIN
TDSU_MIN
TDH_MIN
TCVO
TCCO
DataIn
DataOut
Control_Out
Control_In
CLK
TCDO
TVSU_MIN
TVH_MIN
Ttssu Ttspd
Ttspd
Suspend
Tri-state
Output / IO XXXX Hi-Z
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