AD8145 Data Sheet
Figure 41 shows a specific example of external common-mode
clamping.
GAIN
REF
R
R
0.01µF
0.01µF
+5V
–5V
C
OUT
V
OUT
V+
V+
V–
V–
3
2
1
3
2
1
V
IN
+
R
T
R
S
R
S
HBAT-540C
HBAT-540C
06307-042
Figure 41. External Common-Mode Clamping
The series resistances, R
S
, limit the current in each leg, and the
Schottky diodes limit the voltages on each input to approximately
0.3 V to 0.4 V over the positive power supply, V+, and to 0.3 V
to 0.4 V below the negative power supply, V−. The required
signal bandwidth, the line impedance, and the effective
differential capacitance due to the AD8145 inputs and the
diodes determine the maximum R
S
value.
As with the differential clamp, the series resistors should be
highly matched in value to preserve high frequency CMRR.
PCB LAYOUT CONSIDERATIONS
The two most important issues with regard to PCB layout are
minimizing parasitic signal trace reactances in the feedback
network and providing sufficient thermal relief.
Excessive parasitic reactances in the feedback network cause
excessive peaking in the frequency response of the amplifier
and excessive overshoot in its step response due to a reduction
in phase margin. Oscillation occurs when these parasitic
reactances are increased to a critical point where the phase margin
is reduced to zero. Minimizing these reactances is important to
obtain optimal performance from the AD8145. General high
speed layout practices should be adhered to when applying the
AD8145. Controlled impedance transmission lines are required
for incoming and outgoing signals, referenced to a ground plane.
Typically, the input signals are received over 100 Ω differential
transmission lines. A 100 Ω differential transmission line is readily
realized on the PCB using two well-matched, closely-spaced,
50 Ω single-ended traces that are coupled through the ground
plane. The traces that carry the single-ended output signals are
most often 75 Ω for video signals. Output signal connections
should include series termination resistors that are matched to
the impedance of the line they are driving. When driving high
impedance loads over very short traces, impedance matching is
not required. In these cases, small series resistors should be used to
buffer the capacitance presented by the load.
Broadband power supply decoupling networks should be placed
as close as possible to the supply pins. Small surface-mount ceramic
capacitors are recommended for these networks, and tantalum
capacitors are recommended for bulk supply decoupling.
Minimizing Parasitic Feedback Reactances
Parasitic trace capacitance and inductance are both reduced in
the unity-gain configuration when the feedback trace that connects
the OUT_x pin to the GAIN_x pin is reduced in length. Removing
the copper from the planes below the trace reduces trace capacitance,
but increases trace inductance, because the loop area formed by
the trace and ground plane is increased. A reasonable compromise
that works well is to void all copper directly under the feedback
trace and component pads with margins on each side approximately
equal to one trace width. Combining this technique with minimizing
trace length is effective in keeping parasitic trace reactance in
the unity-gain feedback loop to a minimum.
Maximizing Heat Removal
A square array of thermal vias works well to connect the exposed
paddle to internal ground planes. The vias should be placed
inside the PCB pad that is soldered to the exposed paddle and
should connect to all ground planes.
The AD8145 includes ground connections on its corner pins.
These pins can be used to provide additional heat removal from
the AD8145 by connecting them between the PCB pad that is
soldered to the exposed paddle and a ground plane on the
component side of the board. This layout technique lowers the
overall package thermal resistance. Use of this technique is not
required, but it does result in a lower junction temperature. Designs
must often conform to Design for Manufacturing (DFM) rules
that stipulate how to lay out PCBs in such a way as to facilitate
the manufacturing process. Some of these rules require thermal
relief on pads that connect to planes, and the rules may limit the
extent to which this technique can be used.
Rev. B | Page 18 of 21
Data Sheet AD8145
DRIVING A CAPACITIVE LOAD
The AD8145 typically drives either high impedance loads over
short PCB traces, such as crosspoint switch inputs, or doubly
terminated coaxial cables. A gain of 1 is commonly used in
the high impedance case because a 6 dB transmission line
termination loss is not incurred. A gain of 2 is required when
driving cables to compensate for the 6 dB termination loss.
In all cases, the output must drive the parasitic capacitance of
the feedback loop, conservatively estimated to be 1 pF, in addition
to the capacitance presented by the actual load. When driving a
high impedance input, it is recommended that a small series
resistor be used to buffer the input capacitance of the device
being driven. Clearly, the resistor value must be small enough to
preserve the required bandwidth. In the ideal doubly terminated
cable case, the AD8145 output sees a purely resistive load. In
reality, there is some residual capacitance, which is buffered by
the series termination resistor. Figure 42 illustrates the high
impedance case, and Figure 43 illustrates the cable driving case.
R
S
C
IN
GAIN
REF
R
R
0.01µF
0.01µF
+5V
–5V
C
OUT
V
IN
V
REF
06307-043
Figure 42. Buffering the Input Capacitance of a High-Z Load with G = 1
GAIN
REF
RR
0.01µF
0.01µF
+5V
–5V
C
V
REF
V
IN
R
S
C
S
R
L
OUT
06307-044
Figure 43. Driving a Doubly Terminated Cable with G = 2
POWER-DOWN
The power-down feature can be used to reduce power consumption
when a particular device is not in use and does not place the output
in a high-Z state when asserted. The power-down feature is
asserted when the voltage applied to the power-down pin drops
to approximately 2 V below the positive supply. The AD8145 is
enabled by pulling the power-down pin to the positive supply.
COMPARATORS
In addition to general-purpose applications, the two on-chip
comparators can be used to decode video sync pulses from the
received common-mode voltages or to receive differential digital
information. Built-in hysteresis helps to eliminate false triggers
from noise.
The comparator outputs are designed to drive source-terminated
transmission lines. The source termination technique uses a resistor
in-series with each comparator output such that the sum of the
comparator source resistance (≈20 Ω) and the series resistor
equals the transmission line characteristic impedance. The load
end of the transmission line is high impedance. When the signal
is launched into the source termination, its initial value is one-
half of its source value because its amplitude is divided-by-2 by
the voltage divider formed by the source termination and the
transmission line. At the load, the signal experiences nearly
100% positive reflection due to the high impedance load and
is restored to nearly its full value. This technique is commonly
used in PCB layouts that involve high speed digital logic.
An internal linear voltage regulator derives power for the
comparators from the positive supply; therefore, the AD8145
must always have a minimum positive supply voltage of 4.5 V.
Rev. B | Page 19 of 21
AD8145 Data Sheet
SYNC PULSE EXTRACTION USING COMPARATORS
The AD8145 is particularly useful in KVM applications. KVM
networks transmit and receive computer video signals that typically
comprise red, green, and blue (RGB) video signals and separate
horizontal and vertical sync signals. Because the sync signals are
separate and not embedded in the color signals, it is advantageous
to transmit them using a simple scheme that encodes them among
the three common-mode voltages of the RGB signals. The AD8134
triple differential driver is a natural complement to the AD8145
and performs the sync pulse encoding with the necessary
circuitry on-chip.
The AD8134 encoding equations are given in Equation 4,
Equation 5, and Equation 6.
[ ]
HV
K
VRed
CM
=
2
(4)
[ ]
V2
2
=
K
VGreen
CM
(5)
[ ]
HV
K
VBlue
CM
+=
2
(6)
where:
Red V
CM
, Green V
CM
, and Blue V
CM
are the transmitted common-
mode voltages of the respective color signals.
K is an adjustable gain constant that is set by the AD8134.
V and H are the vertical and horizontal sync pulses, defined
with a weight of −1 when the pulses are in their low states and a
weight of +1 when they are in their high states.
The AD8134 data sheet contains further details regarding the
encoding scheme. Figure 44 illustrates how the AD8145 comparators
can be used to extract the horizontal and vertical sync pulses that
are encoded on the RGB common-mode voltages by the AD8134.
RECEIVED
RED VIDEO
HSYNC
RED CMV
GREEN CMV
BLUE CMV
50Ω
50Ω
1kΩ
1kΩ
VSYNC
RECEIVED
GREEN VIDEO
50Ω
50Ω
RECEIVED
BLUE VIDEO
50Ω
50Ω
R
S
R
S
475Ω
47pF
47pF
06307-045
Figure 44. Extracting Sync Signals from Received Common-Mode Signal
Rev. B | Page 20 of 21

AD8145YCPZ-R2

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Video Amplifiers High Speed Triple Receiver
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