10
Application Information
Bypassing and PC Board Layout
The HCPL-772X/072X optocouplers are extremely easy to use. No external interface circuitry is required because the
HCPL-772X/072X use high-speed CMOS IC technology allowing CMOS logic to be connected directly to the inputs
and outputs.
As shown in Figure 10, the only external components required for proper operation are two bypass capacitors. Ca-
pacitor values should be between 0.01 µF and 0.1 µF. For each capacitor, the total lead length between both ends of
the capacitor and the power-supply pins should not exceed 20 mm. Figure 11 illustrates the recommended printed
circuit board layout for the HPCL-772X/072X.
Figure 10. Recommended printed circuit board layout.
Figure 11. Recommended printed circuit board layout
Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew
Propagation Delay is a gure of merit that describes how quickly a logic signal propagates through a system. The
propaga tion delay from low to high (t
PLH
) is the amount of time required for an input signal to propagate to the
output, causing the output to change from low to high. Similarly, the propagation delay from high to low (t
PHL
) is the
amount of time required for the input signal to propagate to the output, causing the output to change from high to
low. See Figure 12.
Figure 12.
INPUT
t
PLH
t
PHL
OUTPUT
V
I
V
O
10%
90%90%
10%
V
OH
V
OL
0 V
50%
5 V CMOS
2.5 V CMOS
HCPL-0710 fig 13
V
DD2
C1 C2
72X
YWW
V
O
GND
2
V
DD1
V
I
GND
1
C1, C2 = 0.01 µF TO 0.1 µF
7
5
6
8
2
3
4
1
GND
2
C1 C2
NC
V
DD2
NC
V
O
V
DD1
V
I
72X
YWW
C1, C2 = 0.01 µF TO 0.1 µF
GND
1
11
Figure 13. Propagation delay skew waveform.
Figure 14. Parallel data transmission example.
Propagation delay skew repre sents the uncertainty of
where an edge might be after being sent through an op-
tocoupler. Figure 14 shows that there will be uncertainty
in both the data and clock lines. It is important that these
two areas of uncertainty not overlap, otherwise the clock
signal might arrive before all of the data outputs have
settled, or some of the data outputs may start to change
before the clock signal has arrived. From these consider-
ations, the absolute minimum pulse width that can be sent
through optocouplers in a parallel application is twice t
PSK
.
Pulse-width distortion (PWD) is the dierence between
t
PHL
and t
PLH
and often determines the maxi mum data
rate capability of a transmission system. PWD can be
expressed in percent by dividing the PWD (in ns) by the
minimum pulse width (in ns) being trans mitted. Typical-
ly, PWD on the order of 20 - 30% of the minimum pulse
width is tolerable.
Propagation delay skew, t
PSK
, is an important parameter
to con sider in parallel data applications where synchro-
nization of signals on parallel data lines is a concern. If
the parallel data is being sent through a group of opto-
couplers, dierences in propagation delays will cause the
data to arrive at the outputs of the optocouplers at dier-
ent times. If this dierence in propagation delay is large
enough it will determine the maximum rate at which
parallel data can be sent through the optocouplers.
Propagation delay skew is dened as the dierence be-
tween the minimum and maximum propa gation delays,
either t
PLH
or t
PHL
, for any given group of optocoup lers
which are operating under the same conditions (i.e., the
same drive current, supply volt age, output load, and op-
erating temperature). As illustrated in Figure 13, if the in-
puts of a group of optocouplers are switched either ON
or OFF at the same time, t
PSK
is the dierence between
the shortest propagation delay, either t
PLH
or t
PHL
, and
the longest propagation delay, either t
PLH
or t
PHL
.
As mentioned earlier, t
PSK
can determine the maximum
parallel data transmission rate. Figure 14 is the timing
diagram of a typical parallel data application with both
the clock and data lines being sent through the opto-
couplers. The gure shows data and clock signals at the
inputs and outputs of the optocouplers. In this case the
data is assumed to be clocked o of the rising edge of
the clock.
A cautious design should use a slightly longer pulse
width to ensure that any additional uncertainty in the
rest of the circuit does not cause a problem.
The HCPL-772X/072X optocouplers oer the advantage
of guaranteed specications for propagation delays,
pulse-width distortion, and propagation delay skew
over the recommended temperature and power supply
ranges.
50%
50%
t
PSK
V
I
V
O
V
I
V
O
2.5 V,
CMOS
2.5 V,
CMOS
DATA
INPUTS
CLOCK
DATA
OUTPUTS
CLOCK
t
PSK
t
PSK
12
Figure 15. Typical eld bus communication physical model
Digital Field Bus Communication Networks
To date, despite its many draw backs, the 4 - 20 mA ana-
log current loop has been the most widely accepted
standard for implementing process control systems. In
today’s manufacturing environment, however, automat-
ed systems are expected to help manage the process,
not merely monitor it. With the advent of digital eld bus
communication networks such as CC-Link, DeviceNet,
PROFIBUS, and Smart Distributed Systems (SDS), gone
are the days of constrained information. Controllers can
now receive multiple readings from eld devices (sen-
sors, actuators, etc.) in addition to diagnostic informa-
tion.
The physical model for each of these digital eld bus
communica tion networks is very similar as shown in
Figure 15. Each includes one or more buses, an interface
unit, optical isolation, transceiver, and sensing and/or ac-
tuating devices.
CONTROLLER
TRANSCEIVER
OPTICAL
ISOLATION
BUS
INTERFACE
TRANSCEIVER
OPTICAL
ISOLATION
BUS
INTERFACE
TRANSCEIVER
OPTICAL
ISOLATION
BUS
INTERFACE
TRANSCEIVER
OPTICAL
ISOLATION
BUS
INTERFACE
TRANSCEIVER
OPTICAL
ISOLATION
BUS
INTERFACE
FIELD BUS
XXXXXX
YYY
SENSOR
DEVICE
CONFIGURATION
MOTOR
STARTER
MOTOR
CONTROLLER

HCPL-0720-500E

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
High Speed Optocouplers 25MBd 1Ch 150mA
Lifecycle:
New from this manufacturer.
Delivery:
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