© 2008 Microchip Technology Inc. DS22083A-page 11
MCP14628
5.0 APPLICATION INFORMATION
5.1 Bootstrap Capacitor Select
The selection of the bootstrap capacitor is based upon
the total gate charge of the high-side power MOSFET
and the allowable droop in gate drive voltage while the
high-side power MOSFET is conducting.
EQUATION 5-1:
For example:
Q
GATE
= 30 nC
ΔV
DROOP
= 200 mV
C
BOOT
≥ 0.15 uF
A low ESR ceramic capacitor is recommend with a
maximum voltage rating that exceeds the maximum
input voltage, V
CC
, plus the maximum supply voltage,
V
SUPPLY
. It is also recommended that the capacitance
of C
BOOT
not exceed 1.2 uF.
5.2 Decoupling Capacitor
Proper decoupling of the MCP14628 is highly recom-
mended to help ensure reliable operation. This decou-
pling capacitor should be placed as close to the
MCP14628 as possible. The large currents required to
quickly charge the capacitive loads are provided by this
capacitor. A low ESR ceramic capacitor is
recommended.
5.3 Power Dissipation
The power dissipated in the MCP14628 consists of the
power loss associated with the quiescent power and
the gate charge power.
The quiescent power loss can be calculated by the
following equation and is typically negligible compared
to the gate drive power loss.
EQUATION 5-2:
The main power loss occurs from the gate charge
power loss. This power loss can be defined in terms of
both the high-side and low-side power MOSFETs.
EQUATION 5-3:
5.4 PCB Layout
Proper PCB layout is important in a high current, fast
switching circuit to provide proper device operation.
Improper component placement may cause errant
switching, excessive voltage ringing, or circuit latch-up.
There are two important states of the MCP14628
outputs, high and low. Figure 5-1 depicts the current
flow paths when the outputs of the MCP14628 are high
and the power MOSFETs are turned on. Charge
needed to turn on the low-side power MOSFET comes
from the decoupling capacitor C
VCC
. Current flows from
this capacitor through the internal LOWDR circuitry,
into the gate of the low-side power MOSFET, out the
source, into the ground plane, and back to C
VCC
. To
reduce any excess voltage ringing or spiking, the
inductance and area of this current loop must be
minimized.
C
BOOT
Q
GATE
VΔ
DROOP
-----------------------
≥
Where:
C
BOOT
= bootstrap capacitor value
Q
GATE
= total gate charge of the high-
side MOSFET
ΔV
DROOP
= allowable gate drive voltage
droop
P
Q
I
VCC
V
CC
×=
Where:
P
Q
= Quiescent Power Loss
I
VCC
= No Load Bias Current
V
CC
= Bias Voltage
P
GATE
P
HIGHDR
P
LOWDR
+=
P
HIGHDR
V
CC
Q
HIGH
× F
SW
×=
P
LOWDR
V
CC
Q
LOW
× F
SW
×=
Where:
P
GATE
= Total Gate Charge Power Loss
P
HIGHDR
= High-Side Gate Charge Power
Loss
P
LOWDR
= Low-Side Gate Charge Power
Loss
V
CC
= Bias Supply Voltage
Q
HIGH
= High-Side MOSFET Total Gate
Charge
Q
LOW
= Low-Side MOSFET Total GAte
Charge
F
SW
= Switching Frequency
