© 2008 Microchip Technology Inc. DS22083A-page 9
MCP14628
4.0 DETAILED DESCRIPTION
4.1 Device Overview
The MCP14628 is a dual MOSFET gate driver
designed to optimally drive both high-side and low-side
N-channel MOSFETs arranged in a non-isolated
synchronous buck converter topology.
The MCP14628 is capable of suppling 2A (typical)
peak current to the floating high-side power MOSFET
that is connected to the HIGHDR pin. With the excep-
tion of a capacitor, all of the circuitry needed to drive
this high-side N-channel MOSFET is internal to the
MCP14628. A blocking device is placed between the
V
CC
and BOOT pins that allows the bootstrap capacitor
to be charged to V
CC
when the low-side power MOS-
FET is conducting. Refer to Section 5.1, for informa-
tion on determining the proper size of the bootstrap
capacitor. The HIGHDR is also capable of sinking 2A
(typical) peak current.
The LOWDR is capable of sourcing 2A (typical) peak
current and sinking 3.5A (typical) peak current. This
helps ensure that the low-side power MOSFET stays
turned off during the high dv/dt of the PHASE node.
4.2 Adaptive Cross-Conduction
Protection
The MCP14628 prevents cross-conduction power loss
by adaptively ensuring that the high-side and low-side
power MOSFETs are not conducting simultaneously.
When the PWM signal goes low, the HIGHDR is pulled
low and the LOWDR signal is held low until the
HIGHDR reach 1V (typically). At that time, the LOWDR
is allowed to turn on.
4.3 FCCM Mode
The MCP14628 features a diode emulation mode to
enhance the light load system efficiency. The FCCM
pin enables or disables the diode emulating mode. With
the FCCM pin grounded, diode emulation mode is
entered. The forced continuous conduction mode is
entered when the FCCM pin is connected to V
CC
.
In diode emulation mode, the MCP14628 turns off the
low-side power MOSFET when the inductor current
reaches approximately zero even if the PWM input sig-
nal is still low. The LOWDR and HIGHDR both stay low
until the next switching cycle begins. To prevent false
termination of the LOWDR signal, there is a 400 ns
minimum on time, t
LGMIN
, of the LOWDR. This also
ensures that the bootstrap capacitor is fully charged.
In forced continuous conduction mode, the LOWDR of
the MCP14628 does not terminate until the PWM input
signal transitions from a low to a high.
4.4 Tri-State PWM
The PWM input pin of the MCP14628 controls the high
current LOWDR and HIGHDR drive signals. These
signals have three distinct operating modes depending
upon the state of the PWM input signal.
A logic low on the PWM pin cause the LOWDR drive
signal to be high and the HIGHDR drive signal to be
low. When the PWM signal transitions to a logic high,
the LOWDR signal goes low and the HIGHDR signal go
high. To ensure proper operation the PWM input signal
should be capable of a logic low of 0V and a logic high
of 5V.
The third operating mode of the drive signals occurs
when the PWM signal is set to a value equal to V
CC
/2
(typically). When the PWM signal dwells at this voltage
for 175 ns (typically) the MCP14628 disables both
LOWDR and HIGHDR drive signals. Both drive signals
are pulled and held low. Once the PWM signal moves
beyond V
CC
/2, the MCP14628 removes the shutdown
state of the drive signals.
