MAX5152/MAX5153
Power-Down Mode
The MAX5152/MAX5153 feature a software-program-
mable shutdown mode that reduces the typical supply
current to 2µA. The two DACs can be shut down inde-
pendently or simultaneously by using the appropriate
programming word. For instance, enter shutdown mode
(for both DACs) by writing an input control word of
111XXXXXXXXXXXXX (Table 1). In shutdown mode, the
reference inputs and amplifier outputs become high
impedance, and the serial interface remains active.
Data in the input registers is saved, allowing the
MAX5152/MAX5153 to recall the output state prior to
entering shutdown when returning to normal mode. Exit
shutdown by recalling the previous condition or by
updating the DAC with new information. When returning
to normal operation (exiting shutdown), wait 20µs for
output stabilization.
Serial Interface
The MAX5152/MAX5153 3-wire serial interface is com-
patible with both Microwire (Figure 2) and SPI/QSPI
(Figure 3) serial-interface standards. The 16-bit serial
input word consists of an address bit, two control bits,
and 13 bits of data (MSB to LSB) as shown in Figure 4.
The address and control bits determines the response
of the MAX5152/MAX5153, as outlined in Table 1.
The MAX5152/MAX5153’s digital inputs are double
buffered, which allows any of the following: loading the
input register(s) without updating the DAC register(s),
updating the DAC register(s) from the input register(s),
or updating the input and DAC registers concurrently.
The address and control bits allow for the DACs to act
independently.
Low-Power, Dual, 13-Bit Voltage-Output DACs
with Configurable Outputs
10 ______________________________________________________________________________________
D12................D0
MSB LSB
16-BIT SERIAL WORD
FUNCTION
A0 C1 C0
0 0 1 13 bits of DAC data Load input register A; DAC register is unchanged.
0 1 1 13 bits of DAC data
Load all DAC registers from the shift register (start up both DACs with new
data).
1 1 0 13 bits of DAC data Load input register B; all DAC registers are updated.
0 1 0 13 bits of DAC data Load input register A; all DAC registers are updated.
1 0 1 13 bits of DAC data Load input register B; DAC register is unchanged.
0 0 0 1 1 0 x xxxxxxxxx
Shut down DAC A when PDL = 1.
0 0 0 1 0 1 x xxxxxxxxx
Update DAC register B from input register B (start up DAC B with data previ-
ously stored in input register B).
0 0 0 0 0 1 x xxxxxxxxx
Update DAC register A from input register A (start up DAC A with data previ-
ously stored in input register A).
1 1 1 xxxxxxxxxxxxx
Shut down both DACs if PDL = 1.
1 0 0 xxxxxxxxxxxxx
Update both DAC registers from their respective input registers
(start up both DACs with data previously stored in the input registers).
0 0 0 1 1 1 x xxxxxxxxx
Shut down DAC B when PDL = 1.
0 0 0 0 1 0 x xxxxxxxxx UPO goes low (default).
0 0 0 0 1 1 x xxxxxxxxx UPO goes high.
0 0 0 1 0 0 1 xxxxxxxxx Mode 1, DOUT clocked out on SCLK’s rising edge.
0 0 0 1 0 0 0 xxxxxxxxx Mode 0, DOUT clocked out on SCLK’s falling edge (default).
0 0 0 0 0 0 x xxxxxxxxx No operation (NOP).
Table 1. Serial-Interface Programming Commands
“x” = don’t care
Note: When A0, C1, and C0 = “0”, D12, D11, D10, and D9 become control bits.
