MAX5152/MAX5153
Low-Power, Dual, 13-Bit Voltage-Output DACs
with Configurable Outputs
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ELECTRICAL CHARACTERISTICS—MAX5153 (continued)
(V
DD
= +2.7V to +3.6V, V
REFA
= V
REFB
= 1.25V, R
L
= 10kΩ, C
L
= 100pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at T
A
= +25°C, output buffer connected in unity-gain configuration (Figure 9).)
CS = V
DD
, f
DIN
= 100kHz, V
SCLK
= 3Vp-p
(Note 4)
(Note 7)
(Note 7)
ns
Rail-to-rail (Note 6)
To 1/2LSB of full-scale, V
STEP
= 1.25V
40t
CL
SCLK Pulse Width Low
CONDITIONS
ns40t
CH
SCLK Pulse Width High
nV-s5Digital Crosstalk
nV-s5Digital Feedthrough
µs25
Time Required to Exit
Shutdown
µA0 ±0.1I
FB_
Current into FBA or FBB
ns100t
CP
SCLK Clock Period
µA±1
Reference Current in
Shutdown
µA1 8I
DD(SHDN)
Power-Supply Current in
Shutdown
mA0.5 0.6I
DD
Power-Supply Current
V2.7 3.6V
DD
Positive Supply Voltage
ns50t
DS
DIN Setup Time
ns0t
CHS
SCLK Rise to CS Rise Hold
Time
ns40t
CSS
CS Fall to SCLK Rise Setup
Time
C
LOAD
= 200pF
V0 to V
DD
Output Voltage Swing
µs25Output Settling Time
C
LOAD
= 200pF
ns120
V/µs0.75SRVoltage Output Slew Rate
UNITSMIN TYP MAXSYMBOLPARAMETER
t
DO2
SCLK Fall to DOUT Valid
Propagation Delay
ns120t
DO1
SCLK Rise to DOUT Valid
Propagation Delay
ns0t
DH
DIN Hold Time
ns100t
CSW
CS Pulse Width High
ns40t
CS1
CS Rise to SCLK Rise Hold
ns10t
CS0
SCLK Rise to CS Fall Delay
Note 4: SCLK minimum clock period includes rise and fall times.
Note 5: Accuracy is specified from code 40 to code 8191.
Note 6: Accuracy is better than 1LSB for V
OUT
greater than 6mV and less than V
DD
- 100mV. Guaranteed by PSRR test at the end
points.
Note 7: Digital inputs are set to either V
DD
or DGND, code = 0000 hex, R
L
= ∞.
DYNAMIC PERFORMANCE
POWER SUPPLIES
TIMING CHARACTERISTICS
