CY7C1049BNL-17VCT Datasheet CY7C1049BNL-17VCT | P4-P6

CY7C1049BN

Document Number: 001-76449 Rev. *B Page 4 of 15

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device. These user guidelines are not tested.

Storage Temperature ............................... –65 C to +150 C

Ambient Temperature with

Power Applied ......................................... –55 C to +125 C

Supply Voltage on

to Relative GND

[1]

...............................–0.5 V to +7.0 V

DC Voltage Applied to Outputs

in High Z State

[1]

................................–0.5 V to V

+ 0.5 V

DC Input Voltage

[1]

............................ –0.5 V to V

+ 0.5 V

Current into Outputs (LOW) ........................................ 20 mA

Static Discharge Voltage

(per MIL-STD-883, Method 3015) ...........................>2001 V

Latch-Up Current .................................................... >200 mA

Operating Range

Range Ambient Temperature V

Commercial L 0 C to +70 C4.5V–5.5V

Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions

7C1049B-17

Unit

Min Max

Output HIGH Voltage V

= Min., I

= –4.0 mA 2.4 – V

Output LOW Voltage V

= Min., I

= 8.0 mA – 0.4 V

Input HIGH Voltage 2.2 V

+ 0.3 V

Input LOW Voltage

[1]

–0.3 0.3 V

Input Load Current GND < V

< V

–1 +1 A

Output Leakage Current GND < V

OUT

< V

Output Disabled

–1 +1 A

Operating Supply Current V

= Max.,

f = f

MAX

= 1/t

–195mA

SB1

Automatic CE Power-Down

Current – TTL Inputs

Max. V

, CE > V

> V

or V

< V

, f = f

MAX

–40mA

SB2

Automatic CE Power-Down

Current – CMOS Inputs

Max. V

, CE > V

– 0.3V,

> V

– 0.3V or V

< 0.3 V, f = 0,

Commercial

–0.5mA

Note

1. Minimum voltage is–2.0V for pulse durations of less than 20 ns.

CY7C1049BN

Document Number: 001-76449 Rev. *B Page 5 of 15

Capacitance

Parameter

[2]

Description Test Conditions Max. Unit

Input capacitance T

= 25 C, f = 1 MHz, V

= 5.0 V 8 pF

OUT

I/O capacitance 8pF

AC Test Loads and Waveforms

Figure 2. AC Test Loads and Waveforms

90%

10%

3.0V

GND

90%

10%

ALL INPUT PULSES

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

OUTPUT

5 pF

INCLUDING

JIG AND

SCOPE

(a)

(b)

3 ns  3 ns

OUTPUT

R1 481 R1 481

255

167

Equivalent to: VENIN EQUIVALENT

1.73V

THÉ

Data Retention Characteristics

Over the Operating Range

Parameter Description Conditions

[3]

Min Max Unit

for Data Retention 2.0 – V

CCDR

Data Retention Current Commercial L V

= V

= 3.0 V,

CE > V

– 0.3 V,

> V

– 0.3 V or V

< 0.3 V

–200A

CDR

[2]

Chip Deselect to Data Retention

Time

0–ns

[4]

Operation Recovery Time t

–ns

Data Retention Waveform

Figure 3. Data Retention Waveform

3.0 V3.0 V

CDR

> 2V

DATA RETENTION MODE

Notes

2. Tested initially and after any design or process changes that may affect these parameters.

3. No input may exceed V

+ 0.5 V.

4. t

< 3 ns for the -12 and -15 speeds. t

< 5 ns for the -20 and slower speeds.

CY7C1049BN

Document Number: 001-76449 Rev. *B Page 6 of 15

Switching Characteristics

Over the Operating Range

Parameter

[5]

Description

CY7C1049BNL-17

Unit

Min Max

Read Cycle

power

(typical) to the First Access

[6]

1 – ms

Read Cycle Time 17 – ns

Address to Data Valid –17ns

OHA

Data Hold from Address Change 3 – ns

ACE

CE LOW to Data Valid –17ns

DOE

OE LOW to Data Valid –8ns

LZOE

OE LOW to Low Z

[7]

0 – ns

HZOE

OE HIGH to High Z

[7, 8]

–7ns

LZCE

CE LOW to Low Z

[7]

3 – ns

HZCE

CE HIGH to High Z

[7, 8]

–7ns

CE LOW to Power-Up 0 – ns

CE HIGH to Power-Down –17ns

Write Cycle

[9, 10]

Write Cycle Time 17 – ns

SCE

CE LOW to Write End 12 – ns

Address Set-Up to Write End 12 – ns

Address Hold from Write End 0 – ns

Address Set-Up to Write Start 0 – ns

PWE

WE Pulse Width 12 – ns

Data Set-Up to Write End 8 – ns

Data Hold from Write End 0 – ns

LZWE

WE HIGH to Low Z

[7]

3 – ns

HZWE

WE LOW to High Z

[7, 8]

–8ns

Notes

5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I

and 30-pF load capacitance.

6. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. t

power

time has to be provided initially before a read/write operation is started.

7. At any given temperature and voltage condition, t

HZCE

is less than t

LZCE

, t

HZOE

is less than t

LZOE

, and t

HZWE

is less than t

LZWE

for any given device.

8. t

HZOE

, t

HZCE

, and t

HZWE

are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage.

9. The internal write time of the memory is defined by the overlap of CE

LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of

these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.

10. The minimum write cycle time for Write Cycle no. 3 (WE

controlled, OE LOW) is the sum of t

HZWE

and t