CY7C1049BNL-17VCT

CY7C1049BN
Document Number: 001-76449 Rev. *B Page 7 of 15
Switching Waveforms
Figure 4. Read Cycle No. 1
[11, 12]
Figure 5. Read Cycle No. 2 (OE Controlled)
[12, 13]
PREVIOUS DATA VALID DATA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
OE
CE
I
CC
I
SB
IMPEDANCE
ADDRESS
DATA OUT
V
CC
SUPPLY
CURRENT
Notes
11. Device is continuously selected. OE
, CE = V
IL
.
12. WE
is HIGH for read cycle.
13. Address valid prior to or coincident with CE
transition LOW.
CY7C1049BN
Document Number: 001-76449 Rev. *B Page 8 of 15
Figure 6. Write Cycle No. 1 (CE Controlled)
[14, 15]
Figure 7. Write Cycle No. 2 (WE Controlled, OE HIGH during Write)
[14, 15]
Switching Waveforms (continued)
t
WC
DATA VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
t
SCE
CE
ADDRESS
WE
DATA I/O
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 16
Notes
14. Data I/O is high impedance if OE
= V
IH
.
15. If CE
goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
16. During this period the I/Os are in the output state and input signals should not be applied.
CY7C1049BN
Document Number: 001-76449 Rev. *B Page 9 of 15
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW)
[17, 18]
Switching Waveforms (continued)
DATA VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
CE
ADDRESS
WE
DATA I/O
NOTE
19
Notes
17. If CE
goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
18. The minimum write cycle pulse width should be equal to sum of t
SD
and t
HZWE
.
19. During this period the I/Os are in the output state and input signals should not be applied.

CY7C1049BNL-17VCT

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 4M PARALLEL 36SOJ
Lifecycle:
New from this manufacturer.
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