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2) Circuit Operation
The design of the power module (PAM) provide bias
control via Vcntl to achieve optimal RF performance
and power control. The control pin is labeled Vcntl.
Please refer to for the block diagram of this PAM.
Typical Operation Conditions
(Vdd1=Vdd2=Vbias = 3.4V)
Parameter ACPM-7833
Frequency Range 1850 – 1910 MHz
Output Power 28.5 dBm
Vcntl 2.5 V
3) Maximum Ratings
Vdd 5.0V
Drain Current 1.5A
Vcntl 3V
RF input 10 dBm
Temperature -30 to 85°C
Please Note: Avoid Electrostatic Discharge on all I/
O’s.
4) Heat Sinking
The demonstration PC Board provides an adequate
heat sink. Maximum device dissipation should be
kept below 2.5 Watts.
5) Testing
- Signal Source
The CDMA modulated signal for the test is generated
using an Agilent ESG-D4000A (or ESG-D3000A)
Digital Signal Generator with the following settings:
CDMA Setup : Reverse
Spreading: On
Bits/Symbol: 1
Data: PN15
Modulation: OQPSK
Chip Rate: 1.2288 Mcps
High Crest: On
Filter: Std
Phase Polarity: Invert
- ACPR Measurement
The ACPR (and channel power) is measured using
an Avago Technologies 4406 VSA with
corresponding ACPR offsets for IS-98c and JSTD-8.
Averaging of 10 is used for ACPR measurements.
- DC Connection
A DC connector is provided to allow ease of
connection to the I/Os. Wires can be soldered to
the connector pins, or the connector can be
removed and I/Os contacted via clip leads or direct
soldered connections. The wiring of I/Os are listed
in Figures 20 through 23 and the Pin configuration
table. The Vdd sense connections are provided to
allow the use of remote-sensing power supplies of
compensation for PCB traces and cable resistance.
- Device Operation
1) Connect RF Input and Output for the band under
test.
2) Terminate all unused RF ports into 50 Ohms.
3) Connect Vdd1, Vdd2 and Vdd3 supplies
(including remote sensing labeled Vdd1 S, Vdd2
S and Vbias S on the board). Nominal voltage is
3.4V.
4) Connect Vcntl supply and set reference voltage
to the voltage shown in the data packet. Note
that the Vcntl pin is on the back side of the
demonstration board. Please limit Vcntl to not
exceed the corresponding listed “DC Biasing
Condition” in the Data Packet. Note that
increasing Vcntl over the corresponding listed
“DC Biasing Condition” can result in power
decrease and current can exceed the rated limit.
5) Apply RF input power according to the values
listed in “Operation Data” in Data Packet.
6) Power down in opposite sequence.
Input
Vdd1
Passive
Input
Match
On Chip
Inter-stage
Match
Bias Circuit
Passive
Output
Match
Vdd2
Output
Vcntl
Single control bias setting for low Idq
and 40% PAE at Pout = 28.5 dBm
Vbias
Figure 24. Power Module Block Diagram.
