NCP43080
www.onsemi.com
24
V
DS
=V
CS
V
TH_CS _RESET
–(R
SHIFT_CS
*I
CS
)
V
TH_CS_OFF
–(R
SHIFT_CS
*I
CS
)
V
TH_CS_ON
–(R
SHIFT_CS
*I
CS
)
V
DRV
Min ON−time
t
Min OFF−time
t
MIN_TON
t
MIN_TOFF
I
SEC
The t
MIN _TON
and t
MIN_TOFF
are adjustable by R
MIN_TON
and R
MIN_TOFF
resistors, t
MAX_TON
is adjustable by R
MAX_TON
Turn−on delay
Turn−off delay
Primary virtual ZCD
detection delay
Max ON−time
t
MAX _TON
Figure 51. Function of MAX_TON Generator in Heavy Load Condition
Adaptive Gate Driver Clamp and automatic Light Load
Turn−off
As synchronous rectification system significantly
improves efficiency in most of SMPS applications during
medium or full load conditions. However, as the load
reduces into light or no−load conditions the SR MOSFET
driving losses and SR controller consumption become more
critical. The NCP43080 offers two key features that help to
optimize application efficiency under light load and no load
conditions:
1
st
− The driver clamp voltage is modulated and follows
the output load condition. When the output load decreases
the driver clamp voltage decreases as well. Under heavy
load conditions the SR MOSFET’s gate needs to be driven
very hard to optimize the performance and reduce
conduction losses. During light load conditions it is not as
critical to drive the SR MOSFET’s channel into such a low
R
DSON
state. This adaptive gate clamp technique helps to
optimize efficiency during light load conditions especially
in LLC applications where the SR MOSFETs with high
input capacitance are used.
Driver voltage modulation improves the system behavior
when SR controller state is changed in and out of normal or
disable modes. Soft transient between drop at body diode
and drop at MOSFET’s R
DS(on)
only improves stability
during load transients.
2
nd
− In extremely low load conditions or no load
conditions the NCP43080 fully disables driver output and
reduces the internal power consumption when output load
drops below the level where skip−mode takes place.
Both features are controlled by voltage at LLD pin. The
LLD pin voltage characteristic is shown in Figure 52. Driver
voltage clamp is a linear function of the voltage difference
between the VCC and LLD pins from V
LLD_REC
point up to
V
LLD_MAX
. A disable mode is available, where the IC
current consumption is dramatically reduced, when the
difference of V
CC
− V
LLD
voltage drops below V
LLD_DIS
.
When the voltage difference between the V
CC
− V
LLD
pins
increase above V
LLC_REC
the disable mode ends and the IC
regains normal operation. It should be noted that there are
also some time delays to enter and exit from the disable
mode. Time waveforms are shown at Figure 53. There is a
time, t
LLD_DISH
, that the logic ignores changes from disable
mode to normal or reversely. There is also some time
t
LLD_DIS_R
that is needed after an exit from the disable mode
to assure proper internal block biasing before SR controller
starts work normally.
