NCP43080
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Figure 54. NCP43080 Light Load and No Load Detection Principle in Flyback Topologies
RTN
Vmodul
To DRV clamp
To disable
logic
VCC
LLD
GND
NCP43080
Operational waveforms related to the flyback LLD
circuitry are provided in Figure 55. The SR MOSFET drain
voltage drops to ~ 0 V when I
SEC
current is flowing. When
the SR MOSFET is conducting the capacitor C2 charges−up,
causing the difference between the LLD pin and VCC pin to
increase, and drop the LLD pin voltage. As the load
decreases the secondary side currents flows for a shorter a
shorter time. C2 has less time to accumulate charge and the
voltage on the C2 decreases, because it is discharged by R2
and R3. This smaller voltage on C2 will cause the LLD pin
voltage to increase towards V
CC
and the difference between
LLD and V
CC
will go to zero. The output voltage then
directly reduces DRV clamp voltage down from its
maximum level. The DRV is then fully disabled when IC
enters disable mode. The IC exits from disable mode when
difference between LLD voltage and V
CC
increases over
V
LLD_REC
. Resistors R2 and R3 are also used for voltage
level adjustment and with capacitor C3 form low pass filter
that filters relatively high speed ripple at C2. This low pass
filter also reduces speed of state change of the SR controller
from normal to disable mode or reversely. Time constant
should be higher than feedback loop time constant to keep
whole system stable.
Figure 55. NCP43080 Driver Clamp Modulation Waveforms in Flyback Application Entering into Light/No Load
Condition
ISEC
VC2
VDRV
VC3
VLLDMAX
VLLD_REC
VLLD_DIS
VDRVMAX
t
IC enters
disable mode
