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LTC6406IMS8E#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
LTC6406
13
6406fc
APPLICATIONS INFORMATION
Figure 2. AC Test Circuit (–3dB BW Testing)
0.01μF
–
+
1
SHDN
5 6 7 8
16 15
NC
14 13
2
V
+
3
V
–
V
+
V
–
V
+
V
–
4
V
OCM
V
SHDN
V
VOCM
V
OCM
12
V
–
V
–
11
V
+
10
V
+
9
V
–
V
–
V
–
V
–
V
–
V
–
6406 F02
LTC6406
SHDN
0.1μF
0.01μF
R
T
CHOSEN SO
THAT R
T
||R
I
= 100Ω
0.1μF
0.1μF
0.1μF
0.1μF
R
I
R
I
100Ω
100Ω
R
T
50Ω
MINI-CIRCUITS
TCM4-19
MINI-CIRCUITS
TCM4-19
V
+OUT
V
–OUT
V
+
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
+
–
V
IN
•
•
50Ω
•
•
V
TIP
R
T
–IN +OUT +OUTF
+IN –OUT
100k
–OUTF
V
–OUTF
R
F
C
F
V
+OUTF
V
+
C
F
R
F
1.25pF
1.25pF
1.25pF
50Ω
50Ω
V
–IN
V
+IN
output phase balancing to reduce even order harmonics,
and centers each individual output about the potential set
by the V
OCM
pin.
V
OUTCM
= V
OCM
=
V
+OUT
+ V
–OUT
2
The outputs (+OUT and –OUT) of the LTC6406 are capable
of swinging from close to ground to typically 1V below
V
+
. They can source or sink up to approximately 55mA of
current. Each output is designed to directly drive up to 5pF
to ground. Higher load capacitances should be decoupled
with at least 15Ω of series resistance from each output.
Input Pin Protection
The LTC6406 input stage is protected against differential
input voltages which exceed 1.4V by two pairs of series
diodes connected back to back between +IN and –IN. In
addition, the input pins have clamping diodes to either
power supply. If the input pins are over-driven, the current
should be limited to under 10mA to prevent damage to the
IC. The LTC6406 also has clamping diodes to either power
supply on the V
OCM
, V
TIP
and SHDN pins and if driven to
voltages which exceed either supply, they too, should be
current limited to under 10mA.
SHDN Pin
The SHDN pin is a CMOS logic input with a 100k internal
pull-up resistor. If the pin is driven low, the LTC6406 powers
down with Hi-Z outputs. If the pin is left unconnected or
driven high, the part is in normal active operation. Some
care should be taken to control leakage currents at this pin
to prevent inadvertently putting the LTC6406 into shutdown.
The turn-on and turn-off time between the shutdown and
active states are typically less than 1μs.
LTC6406
14
6406fc
APPLICATIONS INFORMATION
General Amplifi er Applications
As levels of integration have increased and correspond-
ingly, system supply voltages decreased, there has been
a need for ADCs to process signals differentially in order
to maintain good signal to noise ratios. These ADCs are
typically supplied from a single supply voltage which can
be as low as 3V, and will have an optimal common mode
input range of 1.25V or 1.5V. The LTC6406 makes interfac-
ing to these ADCs easy, by providing both single-ended
to differential conversion as well as common mode level
shifting. The front page of this data sheet shows a typical
application. The gain to V
OUTDIFF
from V
INM
and V
INP
is:
V
OUTDIFF
= V
+OUT
–V
–OUT
≈
R
F
R
I
•V
INP
–V
INM
()
Note from the above equation, the differential output volt-
age (V
+OUT
– V
–OUT
) is completely independent of input
and output common mode voltages, or the voltage at
the common mode pin. This makes the LTC6406 ideally
suited for preamplifi cation, level shifting and conversion
of single-ended signals to differential output signals in
preparation for driving differential input ADCs.
Effects of Resistor Pair Mismatch
Figure 3 shows a circuit diagram which takes into consid-
eration that real world resistors will not match perfectly.
Assuming infi nite open-loop gain, the differential output
relationship is given by the equation:
V
OUTDIFF
= V
+OUT
–V
–OUT
≅
R
F
R
I
•V
INDIFF
+
Δβ
β
AVG
•V
ICM
–
Δβ
β
AVG
•V
OCM
where:
R
F
is the average of R
F1
, and R
F2
, and R
I
is the average
of R
I1
, and R
I2
.
β
AVG
is defi ned as the average feedback factor from the
outputs to their respective inputs:
β
AVG
=
1
2
•
R
I1
R
I1
+ R
F1
+
R
I2
R
I2
+ R
F2
⎛
⎝
⎜
⎞
⎠
⎟
Δβ is defi ned as the difference in feedback factors:
Δβ =
R
I2
R
I2
+ R
F2
–
R
I1
R
I1
+ R
F1
V
ICM
is defi ned as the average of the two input voltages
V
INP
, and V
INM
(also called the input common mode
voltage):
V
ICM
=
1
2
•V
INP
+ V
INM
()
and V
INDIFF
is defi ned as the difference of the input voltages:
V
INDIFF
= V
INP
– V
INM
V
OCM
is defi ned as the average of the two output voltages
V
+OUT
and V
–OUT
:
V
OCM
=
V
+OUT
+ V
–OUT
2
When the feedback ratios mismatch (Δβ), common mode
to differential conversion occurs.
Setting the differential input to zero (V
INDIFF
= 0), the de-
gree of common mode to differential conversion is given
by the equation:
V
OUTDIFF
= V
+OUT
–V
–OUT
≈ V
ICM
–V
OCM
()
•
Δβ
β
AVG
Figure 3. Real-World Application with Feedback Resistor
Pair Mismatch
–
+
R
F2
V
–OUT
V
+OUT
V
VOCM
V
OCM
6406 F03
R
F1
R
I2
R
I1
+
–
V
INP
–
+
V
INM
V
–IN
V
+IN
LTC6406
15
6406fc
APPLICATIONS INFORMATION
In general, the degree of feedback pair mismatch is a
source of common mode to differential conversion of both
signals and noise. Using 1% resistors or better will mitigate
most problems, and will provide about 34dB worst case of
common mode rejection. Using 0.1% resistors will provide
about 54dB of common mode rejection. A low impedance
ground plane should be used as a reference for both the
input signal source and the V
OCM
pin. Bypassing the V
OCM
with a high quality 0.1μF ceramic capacitor to this ground
plane will further help prevent common mode signals from
being converted to differential signals.
There may be concern on how feedback factor mismatch
affects distortion. Feedback factor mismatch from using
1% resistors or better, has a negligible effect on distortion.
However, in single supply level-shifting applications where
there is a voltage difference between the input common
mode voltage and the output common mode voltage,
resistor mismatch can make the apparent voltage offset
of the amplifi er appear worse than specifi ed.
The apparent input referred offset induced by feedback
factor mismatch is derived from the above equation:
V
OSDIFF(APPARENT)
≈ (V
ICM
– V
OCM
) • Δβ
Using the LTC6406 in a single supply application on a
single 3V supply with 1% resistors, and the input com-
mon mode grounded, with the V
OCM
pin biased at 1.25V,
the worst case DC offset can induce 12.5mV of apparent
offset voltage. With 0.1% resistors, the worst-case ap-
parent offset reduces to 1.25mV.
Input Impedance and Loading Effects
The input impedance looking into the V
INP
or V
INM
input
of Figure 1 depends on whether or not the sources V
INP
and V
INM
are fully differential or not. For balanced input
sources (V
INP
= –V
INM
), the input impedance seen at either
input is simply:
R
INP
= R
INM
= R
I
For single-ended inputs, because of the signal imbalance
at the input, the input impedance actually increases over
the balanced differential case. The input impedance looking
into either input is:
R
INP
= R
INM
=
R
I
1–
1
2
•
R
F
R
I
+ R
F
⎛
⎝
⎜
⎞
⎠
⎟
⎛
⎝
⎜
⎞
⎠
⎟
Input signal sources with non-zero output impedances
can also cause feedback imbalance between the pair of
feedback networks. For the best performance, it is rec-
ommended that the input source output impedance be
compensated for. If input impedance matching is required
by the source, a termination resistor R1 should be chosen
(see Figure 4):
R1=
R
INM
•R
S
R
INM
–R
S
Figure 4. Optimal Compensation for Signal Source Impedance
V
S
+
–
–
+
R
F
R
F
R
I
R
INM
R
S
R
I
R2
R
S
||R1
R1 CHOSEN SO THAT R1||R
INM
= R
S
R2 CHOSEN TO BALANCE R1||R
S
R1
6406 F04
According to Figure 4, the input impedance looking into
the differential amp (R
INM
) refl ects the single-ended source
case, thus:
R
INM
=
R
I
1–
1
2
•
R
F
R
I
+ R
F
⎛
⎝
⎜
⎞
⎠
⎟
⎛
⎝
⎜
⎞
⎠
⎟
R2 is chosen to equal R1||R
S
:
R2 =
R1• R
S
R1+ R
S
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LTC6406IMS8E#TRPBF

Mfr. #:
Buy LTC6406IMS8E#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
High Speed Operational Amplifiers 800 MHz, Low Noise, Rail to Rail Input Differential Amplifier/Driver
Lifecycle:
New from this manufacturer.
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