LTC3633A-2/LTC3633A-3
19
3633a23fb
For more information www.linear.com/LTC3633A-2
APPLICATIONS INFORMATION
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
% Efficiency = 100% – (L1 + L2 + L3 +…)
where L1, L2, etc. are the individual losses as a percent
-
age of input power.
Although all dissipative elements in the circuit produce
losses, three main sources usually account for most of the
losses in LTC3633A-2 circuits: 1) I
2
R losses, 2) switching
losses and quiescent power loss 3) transition losses and
other losses.
1. I
2
R losses are calculated from the DC resistances of the
internal switches, R
SW
, and external inductor, R
L
. In con-
tinuous mode, the average output current flows through
inductor L but is “chopped” between the internal top and
bottom power MOSFET
s. Thus, the series resistance look
-
ing into the SW pin is a function of both top and bottom
MOSFET R
DS(ON)
and the duty cycle (DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus to obtain I
2
R losses:
I
2
R losses = I
OUT
2
(R
SW
+ R
L
)
2. The internal LDO draws power from the SV
IN
input to
regulate the INTV
CC
rail. The total power loss here is
the sum of the switching losses and quiescent current
losses from the control circuitry.
Each time a power MOSFET gate is switched from low
to high to low again, a packet of charge dQ moves from
V
IN
to ground. The resulting dQ/dt is a current out of
INTV
CC
that is typically much larger than the DC control
bias current. In continuous mode, I
GATECHG
= f(Q
T
+ Q
B
),
where Q
T
and Q
B
are the gate charges of the internal
top and bottom power MOSFETs and f is the switching
frequency. For estimation purposes, (Q
T
+ Q
B
) on each
LTC3633A-2 regulator channel is approximately 2.3nC.
To calculate the total power loss from the LDO load,
simply add the gate charge current and quiescent cur
-
rent and multiply by the voltage applied to SV
IN
:
P
LDO
= (I
GATECHG
+ I
Q
) • SV
IN
3. Other “hidden” losses such as transition loss, cop-
per trace resistances, and internal load currents can
account for additional efficiency degradations in the
overall power system. Transition loss arises from the
brief amount of time the top power MOSFET spends
in the saturated region during switch node transitions.
The L
TC3633A-2 internal power devices switch quickly
enough that these losses are not significant compared
to other sources.
Other losses, including diode conduction losses during
dead-time and inductor core losses, generally account
for less than 2% total additional loss.
Thermal Considerations
The LTC3633A-2 requires the exposed package backplane
metal (PGND) to be well soldered to the PC board to
provide good thermal contact. This gives the QFN and
TSSOP packages exceptional thermal properties, which
are necessary to prevent excessive self-heating of the part
in normal operation.
In a majority of applications, the LTC3633A-2 does not
dissipate much heat due to its high efficiency and low
thermal resistance of its exposed-back QFN package.
However, in applications where the LTC3633A-2 is running
at high ambient temperature, high input supply voltage,
high switching frequency, and maximum output current
load, the heat dissipated may exceed the maximum junc
-
tion temperature of the part. If the junction temperature
reaches approximately 150°C, both power switches will
be turned off until temperature returns to 140°C.
To prevent the L
TC3633A-2 from exceeding the maximum
junction temperature of 125°C, the user will need to do
some thermal analysis. The goal of the thermal analysis
is to determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera
-
ture rise is given by:
T
RISE
= P
D
• θ
JA
