ZL30136 Short Form Data Sheet
4
Zarlink Semiconductor Inc.
D2 si/sda I/B Serial Interface Input (LVCMOS). Serial interface data pin. When i2c_en = 0,
this pin acts as the si pin for the serial interface. When i2c_en = 1, this pin acts as
the sda pin (bidirectional) for the I
2
C interface.
D1 so O Serial Interface Output (LVCMOS). Serial interface data output. When i2c_en =
0, this pin acts as the so pin for the serial interface. When i2c_en = 1, this pin is
unused and should be left unconnected.
C2 cs_b/asel0 I
u
Chip Select for SPI/Address Select 0 for I
2
C (LVCMOS). When i2c_en = 0, this
pin acts as the chip select pin (active low) for the serial interface. When i2c_en =
1, this pin acts as the asel0 pin for the I
2
C interface.
E2 int_b O Interrupt Pin (LVCMOS). Indicates a change of device status prompting the
processor to read the enabled interrupt service registers (ISR). This pin is an
open drain, active low and requires an external pulled-up to Vdd.
H2 i2c_en I
u
I
2
C Interface Enable (LVCMOS). If set high, the I
2
C interface is enabled, if set
low the SPI interface is enabled. Internally pull-up to Vdd.
APLL Loop Filter
A5 apll_filter A External Analog PLL Loop Filter Terminal.
B5 filter_ref0 A Analog PLL External Loop Filter Reference.
C5 filter_ref1 A Analog PLL External Loop Filter Reference.
JTAG and Test
G4 tdo O Test Serial Data Out (Output). JTAG serial data is output on this pin on the
falling edge of tck. This pin is held in high impedance state when JTAG scan is
not enabled.
G2 tdi I
u
Test Serial Data In (Input). JTAG serial test instructions and data are shifted in
on this pin. This pin is internally pulled up to Vdd. If this pin is not used then it
should be left unconnected.
G3 trst_b I
u
Test Reset (LVCMOS). Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-
up to ensure that the device is in the normal functional state. This pin is internally
pulled up to Vdd. If this pin is not used then it should be connected to GND.
H3 tck I Test Clock (LVCMOS): Provides the clock to the JTAG test logic. If this pin is not
used then it should be pulled down to GND.
F2 tms I
u
Test Mode Select (LVCMOS). JTAG signal that controls the state transitions of
the TAP controller. This pin is internally pulled up to V
DD
. If this pin is not used
then it should be left unconnected.
Master Clock
H4 osci I Oscillator Master Clock Input (LVCMOS). This input accepts a 20 MHz
reference from a clock oscillator (XO) or crystal XTAL. The stability and accuracy
of the clock at this input determines the free-run accuracy and the long term
holdover stability of the output clocks.
H5 osco O Oscillator Master Clock Output (LVCMOS). This pin must be left unconnected
when the osci pin is connected to a clock oscillator.
Pin # Name
I/O
Type
Description
