5
Rev. 08/19/05 SP6128A Low Voltage, Synchronous Step Down PWM Controller © Copyright 2005 Sipex Corporation
When the overcurrent threshold is exceeded, the
overcurrent comparator sets the fault latch and
terminates the output pulses. The controller
stops switching and goes through a hiccup se-
quence. This prevents excessive power dissipa-
tion in the external power MOSFETs during an
overload condition. An internal delay circuit
prevents that very short and mild overload con-
ditions, that could occur during a load transient,
activate the current limit circuit.
A low power sleep mode can be invoked in the
SP6128A by externally forcing the COMP pin
below 0.3V. Quiescent supply current in sleep
mode is typically less than 30µA. An internal
5µA pull-up current at the COMP pin brings the
SP6128A out of shutdown mode.
An internal 0.8V 1.5% reference allows out-
put voltage adjustment for low voltage appli-
cations.
The SP6128A also includes an accurate under-
voltage lockout that shuts down the controller
when the input voltage falls below 2.7V. Output
overvoltage protection is achieved by turning
off the high side switch and turning on the low
side N-channel MOSFET 100% of the time.
Enable
Low quiescent mode or “Sleep Mode” is initi-
ated by pulling the COMP pin below 0.3V with
an external open-drain or open-collector tran-
sistor. Supply current is reduced to 30µA (typi-
cal) in shutdown. On power-up, assuming that
V
CC
has exceeded the UVLO start threshold
(2.8V), an internal 5µA pull-up current at the
COMP pin brings the SP6128A out of shutdown
mode and ensures start-up. During normal oper-
ating conditions and in absence of a fault, an
internal clamp prevents the COMP pin from
swinging below 0.6V. This guarantees that dur-
ing mild transient conditions, due either to line
or load variations, the SP6128A does not enter
shutdown unless it is externally activated.
During Sleep Mode, the high side and low side
MOSFETS are turned off and the internal soft
start voltage is held low.
UVLO
Assuming that there is not shutdown condition
present, then the voltage on the V
CC
pin deter-
mines operation of the SP6128A. As V
CC
rises,
the UVLO block monitors V
CC
and keeps the
high side and low side MOSFETS off and the
internal SS voltage low until V
CC
reaches 2.8V.
If no faults are present, the SP6128A will ini-
tiate a soft start when V
CC
exceeds 2.8 V.
Hysteresis (about 100mV) in the UVLO com-
parator provides noise immunity at start-up.
Soft Start
Soft start is required on step-down controllers to
prevent excess inrush current through the power
train during start-up. Typically this is managed
by sourcing a controlled current into a timing
capacitor and then using the voltage across this
capacitor to slowly ramp up either the error amp
reference or the error amp output (COMP). The
control loop creates narrow width driver pulses
while the output voltage is low and allows these
pulses to increase to their steady-state duty
cycle as the output voltage increases to its regu-
lated value. As a result of controlling the induc-
tor volt*second product during startup, inrush
current is also controlled.
In the SP6128A the duration of the soft-start is
controlled by an internal timing circuit that
provides a 0.3V/mS slew-rate, which is used
during startup and overcurrent to set the hiccup
time. The SP6128A implements soft-start by
ramping up the error amplifier reference voltage
providing a controlled slew-rate of the output
voltage, thereby preventing overshoot and in-
rush current at power up.
The presence of the output capacitor creates extra
current draw during startup. Simply stated, dV
OUT
/
dt requires an average sustained current in the
output capacitor and this current must be consid-
ered while calculating peak inrush current and
over current thresholds. An approximate expres-
sion to determine the excess inrush current due to
the dV
OUT
/dt of the output capacitor C
OUT
is:
Iinrush = C
OUT
x (0.27 V/ms) x
V
OUT
0.8V
OPERATION: continued
