Low Skew, 1-to-10, HSTL Fanout Buffer
83210
Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 10, 20161
GENERAL DESCRIPTION
The 83210 is a low skew, 1-to-10 HSTL Fanout Buffer.
The class II HSTL outputs are balanced push-pull in design, capable
of delivering 16mA into a 10pF load. This class allows both source
series termination and symmetrically double parallel termination.
FEATURES
Ten single-ended HSTL outputs
One single-ended HSTL clock input
Maximum input frequency: 150MHz
Output skew: 110ps (maximum)
Part-to-part skew: 2ns (maximum)
1.5V power supply
0°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
BLOCK DIAGRAM PIN ASSIGNMENT
32-Lead TQFP
7mm x 7mm x 1.0mm package body
Y package
Top View
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
Q3
Q4
V
DD
VDD
Q5
Q6
GND
VDD
GND
V
DD
nOE
GND
IN
V
DD
GND
GND
Q7
Q8
V
DD
VDD
Q9
GND
GND
GND
Q2
Q1
V
DD
VDD
Q0
GND
GND
ICS83210
Pulldown
Q0
Q1
Q8
Q9
IN
nOE
83210 Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 10, 20162
TABLE 2. PIN CHARACTERISTICS
TABLE 1. PIN DESCRIPTIONS
Number Name Type Description
1, 3, 7, 12, 13,
20, 21, 28, 29
V
DD
Power Power supply pins.
2, 5, 8, 9, 10,
16, 17, 24, 25, 31, 32
GND Power Power supply ground.
4 nOE Input Pulldown
Output enable/disable input pin. When LOW, outputs Qx outputs are
enabled. When HIGH, Qx outputs are disabled low.
LVCMOS/LVTTL interface levels.
5 IN Input Single-ended reference clock input. HSTL interface levels.
11, 14, 15,
18, 19, 22,
23, 26, 27, 30
Q9, Q8, Q7, Q6,
Q5, Q4, Q3, Q2,
Q1, Q0
Output Single-ended HSTL clock outputs.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4pF
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
C
OUT
Output Pin Capacitance 4.5 6 pF
R
OUT
Output Impedance 20
Ω
83210 Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 10, 20163
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, V
DD
= 1.5V ± 8%, TA = 0°C TO 85°C
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, V
DD
= 1.5V ± 8%, TA = 0°C TO 85°C
NOTE: Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
ratings are stress specifications only. Functional operation of
product at these conditions or any conditions beyond those listed
in the DC Characteristics or AC Characteristics is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Power Supply Voltage 1.38 1.5 1.62 V
I
DD
Power Supply Current Outputs Loaded @ 62.5MHz 215 250 mA
I
DDQ
Quiescent Supply Current V
IN
= 0V, outputs disabled 1 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage nOE 0.7*V
DD
V
DD
+ 0.3 V
V
IL
Input Low Voltage nOE -0.3 0.3*V
DD
V
I
IH
Input High Current nOE 150 µA
I
IL
Input Low Current nOE -5 µA
TABLE 3C. HSTL DC CHARACTERISTICS, V
DD
= 1.5V ± 8%, TA = 0°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage IN
V
REF
= 0.75V
0.85 1.8 V
V
IL
Input Low Voltage IN -0.3 0.65 V
V
OH
Output High Voltage I
OH
= -16mA 1.0 V
DD
+ 0.3 V
V
OL
Output Low Voltage I
OL
= 16mA -0.3 0.4 V
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance, θ
JA
75.5°C/W (0 mps)
Storage Temperature, T
STG
-65°C to 150°C

83210AYLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 10 LVCMOS OUT BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
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