71V124SA10TYG8

1
FEBRUARY 2013
DSC-3873/11
2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
©
Features
128K x 8 advanced high-speed CMOS static RAM
JEDEC revolutionary pinout (center power/GND) for
reduced noise
Equal access and cycle times
Commercial: 10/12/15ns
Industrial: 12/15ns
One Chip Select plus one Output Enable pin
Inputs and outputs are LVTTL-compatible
Single 3.3V supply
Low power consumption via chip deselect
Available in a 32-pin 300- and 400-mil Plastic SOJ, and
32-pin Type II TSOP packages.
Functional Block Diagram
Description
The IDT71V124 is a 1,048,576-bit high-speed static RAM organized
as 128K x 8. It is fabricated using high-performance, high-reliability CMOS
technology. This state-of-the-art technology, combined with innovative
circuit design techniques, provides a cost-effective solution for high-speed
memory needs. The JEDEC center power/GND pinout reduces noise
generation and improves system performance.
The IDT71V124 has an output enable pin which operates as fast as
5ns, with address access times as fast as 10ns available. All bidirectional
inputs and outputs of the IDT71V124 are LVTTL-compatible and operation
is from a single 3.3V supply. Fully static asynchronous circuitry is used;
no clocks or refreshes are required for operation.
ADDRESS
DECODER
1,048,576-BIT
MEMORY ARRAY
I/O CONTROL
A
0
A
16
3873 drw 01
8
8
I/O
0
-I/O
7
8
CONTROL
LOGIC
WE
OE
CS
.
3.3V CMOS Static RAM
1 Meg (128K x 8-Bit)
Center Power &
Ground Pinout
IDT71V124SA
2
IDT71V124SA, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges
Truth Table
(1)
Recommended DC Operating
Conditions
Absolute Maximum Ratings
(1)
DC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
Pin Configuration
SOJ and TSOP
Top View
Capacitance
(TA = +25°C, f = 1.0MHz, SOJ package)
5
6
7
8
9
10
11
12
A
0
A
1
A
2
1
2
3
4
32
31
30
29
28
27
26
25
24
23
22
21
A
15
A
3
CS
I/O
1
V
DD
A
14
OE
I/O
7
I/O
6
GND
I/O
5
3873 drw 02
GND
13 20
14 19
15 18
16
A
7
17
I/O
2
I/O
3
WE
A
4
A
5
A
6
A
12
A
11
A
10
A
9
A
8
SO32-2
SO32-3
SO32-4
I/O
0
A
16
A
13
V
DD
I/O
4
.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliabilty.
Symbol Rating Value Unit
V
DD
Supply Voltage Relative
to GND
-0.5 to +4.6 V
V
IN
, V
OUT
Terminal Voltage Relative
to GND
-0.5 to V
DD
+0.5 V
T
A
Commercial
Operating Temperature
-0 to +70
o
C
Industrial
Operating Temperature
-40 to +85
T
BIAS
Temperature Under Bias -55 to +125
o
C
T
STG
Storage Temperature -55 to +125
o
C
P
T
Power Dissipation 1.25 W
I
OUT
DC Output Current 50 mA
3873 tbl 02
NOTE:
1. H = VIH, L = VIL, X = Don't care.
CS OE WE
I/O Function
LLHDATA
OUT
Read Data
LXLDATA
IN
Write Data
L H H High-Z Output Disabled
H X X High-Z DeselectedStandby
3873 tbl 01
NOTE:
1. This parameter is guaranteed by device characterization, but is not production tested.
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 6 pF
C
I/O
I/O Capacitance V
OUT
= 3dV 7 pF
3873 tbl 03
NOTES:
1. For 71V124SA10 only.
2. For all speed grades except 71V124SA10.
3. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle.
4. VIL (min.) = –2V for pulse width less than 5ns, once per cycle.
Symbol Parameter Min. Typ. Max. Unit
V
DD
(1)
Supply Voltage 3.15 3.3 3.6 V
V
DD
(2)
Supply Voltage 3.0 3.3 3.6 V
V
SS
Ground 0 0 0 V
V
IH
Input High Voltage 2.0
____
V
DD
+0.3
(3)
V
V
IL
Input Low Voltage 0.5
(1 )
____
0.8 V
3873 tbl 04
Symbol Parameter Test Conditions Min. Max. Unit
|I
LI
| Input Leakage Current V
DD
= Max., V
IN
=
GND to V
DD
___
A
|I
LO
|
Output Leakage Current V
DD
= Max.,CS
=
V
IH
, V
OUT
=
GND to V
DD
___
A
V
OL
Output Low Voltage I
OL
= 8mA, V
DD
= Min.
___
0.4 V
V
OH
Output High Voltage I
OH
= –4mA, V
DD
= Min. 2.4
___
V
3873 tbl 05
Recommended Operating Tempera-
ture and Supply Voltage
Grade Temperature GND V
DD
Commercial C to +7C 0V See Below
Industrial -4C to +8C 0V See Below
3873 tbl 02a
6.42
IDT71V124SA, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges
3
+1.5V
50Ω
I/O
Z
0
=50Ω
3873 drw 03
30pF
.
*Including jig and scope capacitance.
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
Figure 1. AC Test Load
AC Test Conditions
DC Electrical Characteristics
(1, 2)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V)
3873 drw 04
320Ω
350Ω5pF*
DATA
OUT
3.3V
NOTES:
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and VDD–0.2V (High).
3. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
Symbol Parameter
71V124SA10 71V124SA12 71V124SA15
Unit
Commercial Com'l Ind Com'l Ind
I
CC
Dynamic Operating Current
CS <
V
LC
, Outputs Open, V
DD
= Max., f = f
MAX
(3)
145 130 140 100 120
mA
I
SB
Dynamic Standby Power Supply Current
CS >
V
HC
, Outputs Open, V
DD
= Max., f = f
MAX
(3)
45 40 40 35 40
mA
I
SB1
Full Standby Power Supply Current (static)
CS >
V
HC
, Outputs Open, V
DD
= Max., f = 0
(3)
10 10 10 10 10
mA
3873 tbl 06
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1 and 2
3873 tbl 07

71V124SA10TYG8

Mfr. #:
Manufacturer:
IDT
Description:
SRAM 128Kx8 ASYNCHRONOUS 3.3V STATIC RAM
Lifecycle:
New from this manufacturer.
Delivery:
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