–3–REV. 0
AD5203
NOTES
1
Typicals represent average readings at +25°C and V
DD
= +5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27 test circuit. I
W
= V
DD
/R
for both V
DD
= +3 V or V
DD
= +5 V.
3
V
AB
= V
DD
, Wiper (V
W
) = No connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 26 test circuit.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the AX terminals. All AX terminals are open-circuited in shutdown mode.
8
Worst case supply current consumed when all logic-input levels set at 2.4 V, standard characteristic of CMOS logic. See Figure 19 for a plot of I
DD
vs. logic voltage
inputs result in minimum power dissipation.
9
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
10
All dynamic characteristics use V
DD
= +5 V.
11
Measured at a V
W
pin where an adjacent V
W
pin is making a full-scale voltage change.
12
See timing diagrams for location of measured values. All input control voltages are specified with t
R
= t
F
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using both V
DD
= +3 V or +5 V. Input logic should have a 1 V/ µs minimum slew rate.
13
Propagation delay depends on value of V
DD
, R
L
and C
L
. See Operation section.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C, unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +8 V
V
A
, V
B
, V
W
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V
DD
I
AB
, I
AW
, I
BW
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Digital Input and Output Voltage to GND . . . . . . . 0 V, +8 V
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (T
J
MAX) . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
Package Power Dissipation . . . . . . . . . . . . . . (T
J
max–T
A
)/θ
JA
Thermal Resistance θ
JA
P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
TSSOP-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143°C/W
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Table I. Serial-Data Word Format
ADDR DATA
B7 B6 B5 B4 B3 B2 B1 B0
A1 A0 D5 D4 D3 D2 D1 D0
MSB LSB MSB LSB
2
7
2
6
2
5
2
0
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5203 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
SDI
CLK
CS
V
OUT
1
0
1
0
1
0
V
DD
0V
D0D1D2D3D4D5A0A1
DAC REGISTER LOAD
Figure 1a. Timing Diagram
CLK
V
OUT
1
0
1
0
1
0
V
DD
0V
SDI
(DATA IN)
SDO
(DATA OUT)
CS
1
0
Ax OR Dx Ax OR Dx
A'x OR D'x
t
DS
t
DH
t
PD MAX
t
PD MIN
t
CH
t
CS1
t
CL
t
CSS
t
CSH
61 LSB
6 1 LSB ERROR BAND
t
CSW
t
S
A'x OR D'x
Figure 1b. Detail Timing Diagram
V
OUT
V
DD
0V
RS
1
0
61 LSB
61 LSB ERROR BAND
t
S
t
RS
Figure 1c. Reset Timing Diagram
