4
ICS9250-10
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
E018
noitidnoC
noitpmusnocylppusV5.2xaM
,sdaolpacetercsidxaM
V526.2=2qddV
DNGro3qddV=stupnicitatsllA
noitpmusnocylppusV5.2xaM
,sdaolpacetercsidxaM
V564.3=2qddV
DNGro3qddV=stupnicitatsllA
edoMnwodrewoP
0=#NWDRWP(
Am01Am01
zHM66evitcAlluF
01=0,1LES
Am07Am082
zHM001evitcAlluF
11=0,1LES
Am001Am082
Maximum Allowed Current
5
ICS9250-10
1. The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controler (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Read:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Write:
6
ICS9250-10
tiBnoitpitcseDDWP
7tiB )lamronetarepootkcolc0ebotsdeeN(TIBDEVRESERSCI0
6tiB )lamronetarepootkcolc0ebotsdeeN(TIBDEVRESERSCI0
5tiB )lamronetarepootkcolc0ebotsdeeN(TIBDEVRESERSCI0
tiB
)0,3,4(
)0,3,4(tiB
KLCUPC
zHM
MARDS
zHM
66V3
zHM
KLCICP
zHM
XXXX
1etoN
0SF
)WH(
3LES
)4tiB(
2LES
)3tiB(
1LES
)0tiB(
0000 76.6600176.6633.33
0001 76.0760176.0733.53
0010 66.4721176.4733.73
0011 66.2842166.2833.14
0100 5.3652.595.3657.13
0101 76.8630176.8633.43
0110 76.2790176.2733.63
0111 66.8833166.8833.44
1000 00100176.6633.33
100 1 60160176.0733.53
10 10 21121176.4733.73
10 11 42142166.2833.14
1100 52.5952.595.3657.13
1101 30130176.8633.43
1110 90190176.2733.63
1111 33133166.8833.44
2tiB)noitarepokcolclamronrof1ebotsdeeN(desutoN 1
1tiB)noitarepokcolclamronrof1ebotsdeeN(desutoN 1
Byte 5:ICS Reserved Functionality and frequency select register (Default=0)
Note1: Default at power-up will be for latched logic inputs to define frequency, as diplayed by Bit 3.

ICS9250CF-10

Mfr. #:
Manufacturer:
Description:
IC FREQ TIMING GENERATOR 56-SSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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