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ICS9250CF-10

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
7
ICS9250-10
Byte 0: Control Register
(1 = enable, 0 = disable)
Byte 1: Control Register
(1 = enable, 0 = disable)
Byte 2: Control Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured
at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
tiB#niPemaNDWPnoitpircseD
7tiBdevreseR0)evitcanI/evitcA(
6tiBdevreseR0)evitcanI/evitcA(
5tiBdevreseR0)evitcanI/evitcA(
4tiBdevreseR1)evitcanI/evitcA(
3tiB
murtcepSdaerpS
)ffO=0/nO=1(
1)evitcanI/evitcA(
2tiB621zHM841)evitcanI/evitcA(
1tiB520zHM841)evitcanI/evitcA(
0tiB942KLCUPC1)evitcanI/evitcA(
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7tiB637MARDS1)evitcanI/evitcA(
6tiB736MARDS1)evitcanI/evitcA(
5tiB935MARDS1)evitcanI/evitcA(
4tiB044MARDS1)evitcanI/evitcA(
3tiB243MARDS1)evitcanI/evitcA(
2tiB342MARDS1)evitcanI/evitcA(
1tiB541MARDS1)evitcanI/evitcA(
0tiB640MARDS1)evitcanI/evitcA(
tiB#niPemaNDWPnoitpircseD
7tiB027KLCICP1)evitcanI/evitcA(
6tiB916KLCICP1)evitcanI/evitcA(
5tiB815KLCICP1)evitcanI/evitcA(
4tiB614KLCICP1)evitcanI/evitcA(
3tiB513KLCICP1)evitcanI/evitcA(
2tiB312KLCICP1)evitcanI/evitcA(
1tiB211KLCICP1)evitcanI/evitcA(
0tiB- devreseR0)evitcanI/evitcA(
8
ICS9250-10
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Byte 3: Reserved Register
(1 = enable, 0 = disable)
Byte 4: Reserved Register
(1 = enable, 0 = disable)
tiB#niPemaNDWPnoitpircseD
7tiB- devreseR0)evitcanI/evitcA(
6tiB- devreseR0)evitcanI/evitcA(
5tiB- devreseR0)evitcanI/evitcA(
4tiB- devreseR0)evitcanI/evitcA(
3tiB- devreseR0)evitcanI/evitcA(
2tiB- devreseR0)evitcanI/evitcA(
1tiB- devreseR0)evitcanI/evitcA(
0tiB- devreseR0)evitcanI/evitcA(
tiB#niPemaNDWPnoitpircseD
7tiB- devreseR0)evitcanI/evitcA(
6tiB- devreseR0)evitcanI/evitcA(
5tiB- devreseR0)evitcanI/evitcA(
4tiB- devreseR0)evitcanI/evitcA(
3tiB- devreseR0)evitcanI/evitcA(
2tiB- devreseR0)evitcanI/evitcA(
1tiB- devreseR0)evitcanI/evitcA(
0tiB- devreseR0)evitcanI/evitcA(
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured
at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
9
ICS9250-10
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
Input High Voltage V
IH
2V
DD
+0.3 V
Input Low Voltage V
IL
V
SS
-0.3 0.8 V
Input High Current I
IH
V
IN
= V
DD
-5 5
µ
A
I
IL1
V
IN
= 0 V; Inputs with no pull-up resistors -5 2
I
IL2
V
IN
= 0 V; Inputs with pull-up resistors -200 -100
C
L
= 0 pF; Select @ 66 MHz 97 110
C
L
= 0 pF; Select @ 100 MHz 91 105
C
L
= 0 pF; Select @ 133 MHz 100 130
C
L
= Max loads; Select @ 66 MHz 275 310
C
L
= Max loads; Select @ 100 MHz 267 300
C
L
= Max loads; Select @ 133 MHz 278 350
C
L
= 0 pF; Select @ 66 MHz 8 10
C
L
= 0 pF; Select @ 100 MHz 11 15
C
L
= 0 pF; Select @ 133 MHz 13 20
C
L
= Max loads; Select @ 66 MHz 22 70
C
L
= Max loads; Select @ 100 MHz 31 100
C
L
= Max loads; Select @ 133 MHz 37 130
I
DD3.3PD
C
L
= Max loads
220
400
I
DD.25PD
Input address VDD or GND
<1 10
Input Frequency F
i
V
DD
= 3.3 V 12 14.32 16 MH
Pin Inductance L
pin
7nH
C
IN
Logic Inputs 5 pF
C
OUT
Output pin capacitance 6 pF
C
INX
X1 & X2 pins 27 45 pF
Transition time
1
T
trans
To 1st crossing of target frequency 5 ms
Settling time
1
T
s
From 1st crossing to 1% target frequency 5 ms
Clk Stabilization
1
T
ST AB
From V
DD
= 3.3 V to 1% target frequency 5 ms
t
PZH
,t
PZL
Output enable delay (all outputs) 1 10 ns
t
PHZ
,t
PLZ
Output disable delay (all outputs) 1 10 ns
1
Guaranteed by design, not 100% tested in production.
Input Low Current µA
mA
mA
I
DD3.3OP
Delay
1
mA
mA
Input Capacitance
1
I
DD2.5OP
µAPowerdown Current
Operating Supply
Current
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

ICS9250CF-10

Mfr. #:
Buy ICS9250CF-10
Manufacturer:
Description:
IC FREQ TIMING GENERATOR 56-SSOP
Lifecycle:
New from this manufacturer.
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