NCV8503 Series
http://onsemi.com
10
Voltage Adjust
Figure 19 shows the device setup for a user configurable
output voltage. The feedback to the V
ADJ
pin is taken from
a voltage divider referenced to the output voltage. The loop
is balanced around the Unity Gain threshold (1.30 V
typical). JEDEC standard JESD78 requires −100 mA trigger
test conditions. V
ADJ
conforms to −75 mA test conditions.
Figure 19. Adjustable Output
Voltage
V
OUT
V
ADJ
NCV8503
15 k
5.1 k
C
OUT
≈5.0 V
1.28 V
APPLICATION NOTES
FLAG MONITOR
Figure 20 shows the FLAG Monitor waveforms as a result
of the circuit depicted in Figure 18. As the input voltage falls
(V
MON
), the Monitor threshold is crossed. This causes the
voltage on the FLAG
output to go low.
Figure 20. FLAG Monitor Circuit Waveform
MON
MON
Flag Monitor
Ref. Voltage
FLAG
SETTING THE DELAY TIME
The delay time is controlled by the Reset Delay Low
Voltage, Delay Switching Threshold, and the Delay Charge
Current. The delay follows the equation:
t
DELAY
+
ƪ
C
DELAY
(V
dt
* Reset Delay Low Voltage)
ƫ
Delay Charge Current
Example:
Using C
DELAY
= 33 nF.
Assume reset Delay Low Voltage = 0.
Use the typical value for V
dt
= 1.8 V (2.5 V, 3.3 V, and
5.0 V options).
Use the typical value for Delay Charge Current = 4.2 mA.
t
DELAY
+
ƪ
33 nF(1.8 * 0)
ƫ
4.2 mA
+ 14 ms
STABILITY CONSIDERATIONS
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: start−up
delay, load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (−25°C to −40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturers data sheet usually provides this information.
The value for the output capacitor C
OUT
shown in Figure 21
should work for most applications, however it is not
necessarily the optimized solution.
Figure 21. Test and Application Circuit Showing
Output Compensation
V
IN
V
OUT
C
OUT
**
33 mF
R
RST
RESET
C
IN
*
0.1 mF
NCV8503
*C
IN
required if regulator is located far from the power supply filter
**C
OUT
required for stability. Capacitor must operate at minimum
temperature expected
