74HC245
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4
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol Parameter Test Conditions
V
CC
V
–55 to
25_C
v 85_C v 125_C
Unit
V
IH
Minimum High−Level Input Voltage V
out
= V
CC
– 0.1 V
|I
out
| v 20 mA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
V
IL
Maximum Low−Level Input Voltage V
out
= 0.1 V
|I
out
| v 20 mA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IH
|I
out
| v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
in
= V
IH
|I
out
| v 2.4 mA
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IL
|I
out
| v 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IL
|I
out
| v 2.4 mA
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
I
in
Maximum Input Leakage Current V
in
= V
CC
or GND 6.0 ±0.1 ±1.0 ±1.0
mA
I
OZ
Maximum Three−State Leakage
Current
Output in High−Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
6.0 ±0.5 ±5.0 ±10
mA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
I
out
= 0 mA
6.0 4.0 40 40
mA
6. Information on typical parametric values and high frequency or heavy load considerations can be found in the ON Semiconductor
High−Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Symbol Parameter
V
CC
V
Guaranteed Limit
Unit
–55 to
25_C
v 85_C v 125_C
t
PLH
,
t
PHL
Maximum Propagation Delay,
A to B, B to A
(Figures 1 and 3)
2.0
3.0
4.5
6.0
75
55
15
13
95
70
19
16
110
80
22
19
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay,
Direction or Output Enable to A or B
(Figures 2 and 4)
2.0
3.0
4.5
6.0
110
90
22
19
140
110
28
24
165
130
33
28
ns
t
PZL
,
t
PZH
Maximum Propagation Delay,
Output Enable to A or B
(Figures 2 and 4)
2.0
3.0
4.5
6.0
110
90
22
19
140
110
28
24
165
130
33
28
ns
t
TLH
,
t
THL
Maximum Output Transition Time,
Any Output
(Figures 1 and 3)
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
ns
C
in
Maximum Input Capacitance (Pin 1 or Pin 19) − 10 10 10 pF
C
out
Maximum Three−State I/O Capacitance
(I/O in High−Impedance State)
− 15 15 15 pF
7. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed
CMOS Data Book (DL129/D).
C
PD
Power Dissipation Capacitance (Per Transceiver Channel) (Note 8)
Typical @ 25°C, V
CC
= 5.0 V
pF
40
8. Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
. For load considerations, see the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
