PCA9518D,118

1. General description

The PCA9518 is a BiCMOS integrated circuit intended for application in I

2

C-bus and

SMBus systems.

While retaining all the operating modes and features of the I

2

C-bus system, it permits

extension of the I

2

C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus

enabling virtually an unlimited number of buses of 400 pF.

using the expansion pins.

The PCA9518 is a wider voltage range (2.3 V to 3.6 V) version of the PCA9518 and also

improves partial power-down performance, keeping I

state when V

is below 2.0 V.

A PCA9518 cluster cannot be put in series with a PCA9515/16 or with another

PCA9518 cluster. Multiple PCA9518 devices can be grouped with other PCA9518

devices into any size cluster thanks to the EXPxxxn pins that allow the I

C-bus signals to

PCA9518 cluster. When this ‘buffered LOW’ is applied to a PCA9515 and PCA9516 or

separate PCA9518 cluster (not connected via the EXPxxxn pins) in series, the second

PCA9515 and PCA9516 or PCA9518 cluster will not recognize it as a ‘regular LOW’ and

will not propagate it as a ‘buffered LOW’ again. The PCA9510/9511/9513/9514 and

PCA9512 cannot be used in series with the PCA9515 and PCA9516 or PCA9518, but can

be used in series with themselves since they use shifting instead of static offsets to avoid

lock-up conditions.

PCA9518

Expandable 5-channel I

2

C-bus hub

Expandable 5-channel I

C-bus hub

2. Features

n Expandable 5 channel, bidirectional buffer

n I

n Active HIGH individual repeater enable inputs

n Open-drain input/outputs

n Lock-up free operation

n Supports arbitration and clock stretching across the repeater

n 0 Hz to 400 kHz clock frequency

2

n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

n Package offerings: SO20 and TSSOP20

3. Ordering information

2. The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater.

Expandable 5-channel I

C-bus hub

4. Block diagram

A more detailed view of Figure 1 buffer is shown in Figure 2.

The output pull-down voltage of each internal buffer is set for approximately 0.5 V, while

the input threshold of each internal buffer is set about 0.07 V lower, when the output is

internally driven LOW. This prevents a lock-up condition from occurring.