M68AW256M
4/23
SUMMARY DESCRIPTION
The M68AW256M is a 4 Mbit (4,194,304 bit)
CMOS SRAM, organized as 262,144 words by 16
bits. The device features fully static operation re-
quiring no external clocks or timing strobes, with
equal address access and cycle times. It requires
a single 2.7 to 3.6V supply. This device has an au-
tomatic power-down feature, reducing the power
consumption by over 99% when deselected.
The M68AW256 is available in TFBGA48 (6x8mm
- 6x8 active ball array, 0.75mm pitch), TFBGA48
(7x8mm - 6x8 active ball array, 0.75 mm pitch) and
in TSOP44 Type II packages.
In addition to the standard version, both packages
are also available in Lead-free version, in compli-
ance with the JEDEC Std J-STD-020B, the ST
ECOPACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive.
All packages are compliant with Lead-free solder-
ing processes.
Figure 2. Logic Diagram Table 1. Signal Names
AI04870b
18
A0-A17
W
DQ0-DQ15
V
CC
M68AW256M
G
16
E
UB
LB
V
SS
A0-A17 Address Inputs
DQ0-DQ15 Data Input/Output
E
Chip Enable
G
Output Enable
W
Write Enable
UB
Upper Byte Enable Input
LB
Lower Byte Enable Input
V
CC
Supply Voltage
V
SS
Ground
NC Not Connected Internally
DU Don’t Use as Internally Connected
