8-OUTPUT 3.3V PCIE CLOCK GENERATOR 4 DECEMBER 1, 2016
9FGL08 DATASHEET
Pin Descriptions, cont.
Test Loads
Alternate Terminations
The 9FGL family can easily drive LVPECL, LVDS, and CML logic. See “AN-891 Driving LVPECL, LVDS, and CML Logic with
IDT's "Universal" Low-Power HCSL Outputs” for details.
PIN # PIN NAME TYPE DESCRIPTION
40 GND GND Ground pin.
41 DIF6 OUT Differential true clock output
42 DIF6# OUT Differential Complementary clock output
43 vOE6# IN
Active low input for enabling DIF pair 6. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
44 DIF7 OUT Differential true clock output
45 DIF7# OUT Differential Complementary clock output
46 vOE7# IN
Active low input for enabling DIF pair 7. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
47 VDDIO PWR Power supply for differential outputs
48 ^CKPWRGD_PD# IN
Input notifies device to sample latched inputs and start up on first high
assertion. Low enters Power Down Mode, subsequent high assertions exit
Power Down Mode. This pin has internal pull-up resistor.
49 EPAD GND
Connect to Ground.
Rs
Rs
Low-Power Differential Output Test Load
2pF 2pF
5 inches
Zo=100ohm
Note: The device can drive transmission line lengths greater
than those specified by the PCIe SIG
Terminations
Device Zo ()Rs ()
9FGL0841 100 None needed
9FGL0851 100 7.5
9FGL08P1 100 Prog.
9FGL0841 85 N/A
9FGL0851 85 None needed
9FGL08P1 85 Prog.
DECEMBER 1, 2016 5 8-OUTPUT 3.3V PCIE CLOCK GENERATOR
9FGL08 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9FGL08. These ratings, which are standard values
for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended
operating temperature range.
Electrical Characteristics–SMBus Parameters
Electrical Characteristics–Current Consumption
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Supply Voltage VDDx -0.5 4.6 V 1,2
Input Voltage V
IN
-0.5 V
DD
+0.5 V 1,3
Input High Voltage, SMBus V
IHSMB
SMBus clock and data pins 3.9 V 1
Storage Temperature Ts -65 150 °C 1
Junction Temperature Tj 125 °C 1
Input ESD protection ESD prot Human Body Model 2500 V 1
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 4.6V.
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
SMBus Input Low Voltage V
ILSMB
V
DDSMB
= 3.3V 0.8 V
SMBus Input High Voltage V
IHSMB
V
DDSMB
= 3.3V 2.1 3.6 V
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V
SMBus Sink Current I
PULLUP
@ V
OL
4mA
Nominal Bus Voltage V
DDSMB
2.7 3.6 V
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency
f
SMB
SMBus operating frequency 500 kHz 2
1
Guaranteed by design and characterization, not 100% tested in production.
2.
The device must be powered up for the SMBus to function.
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
I
DDAOP
VDDA, All outputs active @100MHz 13 18 mA
I
DDOP
All VDD, except VDDA and VDDIO, All outputs
active @100MHz
19
26 mA
I
DDIOOP
VDDIO, All outputs active @100MHz
31
40 mA
I
DDAP
D
VDDA, DIF outputs off, REF output running
0.9
1.5 mA 1
I
DDPD
All VDD, except VDDA and VDDIO,
DIF outputs off, REF output running
6.5 9mA1
I
DDIOP
D
VDDIO, DIF outputs off, REF output running 0.05 0.1 mA 1
I
DDAP
D
VDDA, all outputs off 0.9 1.5 mA
I
DDPD
All VDD, except VDDA and VDDIO, all outputs off
2.4 3mA
I
DDIOPD
VDDIO, all outputs off 0.05 0.1 mA
1
This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1)
Powerdown Current
(Power down state and
Byte 3, bit 5 = '0')
Operating Supply Current
Wake-on-LAN Current
(Power down state and
Byte 3, bit 5 = '1')
8-OUTPUT 3.3V PCIE CLOCK GENERATOR 6 DECEMBER 1, 2016
9FGL08 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Supply Voltage VDDxxx
Supply voltage for core, analog and single-ended
LVCMOS outputs.
3.135 3.3 3.465 V
IO Supply Voltage VDDIO Supply voltage for differential Low Power outputs. 0.9975 1.05-3.3 3.465 V
Ambient Operating
Temperature
T
AMB
Industrial range -40 25 85 °C
Input High Voltage V
IH
0.75 V
DDx
V
DDx
+ 0.3 V
Input Low Voltage V
IL
-0.3 0.25 V
DDx
V
Input High Voltage V
IHtri
0.75 V
DDx
V
DD
+ 0.3 V
Input Mid Voltage V
IMtri
0.4 V
DDx
0.5 V
DDx
0.6 V
DDx
V
Input Low Voltage V
ILtri
-0.3 0.25 V
DDx
V
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
-50 50 uA
Input Frequency F
in
XTAL, or X1 input 8 25 40 MHz 4
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
OUT
Output pin capacitance 6 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
0.3 1.8 ms 1,2
SS Modulation Frequency f
MO
D
(Triangular Modulation) 30 31.6 33 kHz 1
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
12 3clocks1,3
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
300 us 1,3
Tfall t
F
Fall time of single-ended control inputs 5 ns 1,2
Trise t
R
Rise time of single-ended control inputs 5 ns 1,2
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
Input Current
4
The 9FGLxxP1 devices can be programmed for various input frequencies from 8 to 40MHz. The 9FGLxx41/51 devices use 25MHz.
Capacitance
3
Time from deassertion until outputs are >200 mV
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)

9FGL0841BKILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products 8 O/P PCIE Gen 1-2-3 Clock Gen 100 Ohm
Lifecycle:
New from this manufacturer.
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