LT1715
10
1715fa
Figure 2. Typical Topside Metal for Multilayer PCB Layouts
1715 F02
APPLICATIONS INFORMATION
When both input signals are above the positive common
mode limit, the input stage will get debiased and the output
polarity will be random. However, the internal hysteresis
will hold the output to a valid logic level. When at least one
of the inputs returns to within the common mode limits,
recovery from this state will take as long as 1μs.
The propagation delay does not increase signifi cantly when
driven with large differential voltages, but with low levels
of overdrive, an apparent increase may be seen with large
source resistances due to an RC delay caused by the 2pF
typical input capacitance.
Input Protection
The input stage is protected against damage from large
differential signals, up to and beyond a differential voltage
equal to the supply voltage, limited only by the absolute
maximum currents noted. External input protection cir-
cuitry is only needed if currents would otherwise exceed
these absolute maximums. The internal catch diodes can
conduct current up to these rated maximums without
latchup, even when the supply voltages are at the absolute
maximum ratings.
The LT1715 input stage has general purpose internal ESD
protection for the human body model. For use as a line
receiver, additional external protection may be required.
As with most integrated circuits, the level of immunity to
ESD is much greater when residing on a printed circuit
board where the power supply decoupling capacitance will
limit the voltage rise caused by an ESD pulse.
Input Bias Current
Input bias current is measured with both inputs held at
1V. As with any PNP differential input stage, the LT1715
bias current fl ows out of the device. It will go to zero on
the higher of the two inputs and double on the lower
of the two inputs. With more than two diode drops of
differential input voltage, the LT1715’s input protection
circuitry activates, and current out of the lower input will
increase an additional 30% and there will be a small bias
current into the higher of the two input pins, of 4μA or
less. See the Typical Performance curve “Input Current
vs Differential Input Voltage.”
High Speed Design Considerations
Application of high speed comparators is often plagued by
oscillations. The LT1715 has 4mV of internal hysteresis,
which will prevent oscillations as long as parasitic output
to input feedback is kept below 4mV. However, with the
2V/ns slew rate of the LT1715 outputs, a 4mV step can
be created at a 100Ω input source with only 0.02pF of
output to input coupling. The LT1715’s pinout has been
arranged to minimize problems by placing the sensitive
inputs away from the outputs, shielded by the power rails.
The input and output traces of the circuit board should
also be separated, and the requisite level of isolation is
readily achieved if a topside ground plane runs between
the output and the inputs. For multilayer boards where the
ground plane is internal, a topside ground or supply trace
should be run between the inputs and the output.
The ground pin of the LT1715 can disturb the ground plane
potential while toggling due to the extremely fast on and
off times of the output stage. Therefore, using a ground
for input termination or fi ltering that is separate from the
LT1715 Pin 6 ground can be highly benefi cial. For example,
a ground plane tied to Pin 6 and directly adjacent to a 1"
long input trace can capacitively couple 4mV of disturbance
into the input. In this scenario, cutting the ground plane
between the GND pin and the inputs will cut the capacitance
and the disturbance down substantially.
Figure 2 shows a typical topside layout of the LT1715
on such a multilayer board. Shown is the topside metal
etch including traces, pin escape vias, and the land pads
for an MS10 LT1715 and its adjacent X7R 10nF bypass
capacitors in the 0805 case.
