LT1715
9
1715fa
Power Supply Confi gurations
The LT1715 has separate supply pins for the input and
output stages that allow fl exible operation, accommodating
separate voltage ranges for the analog input and the output
logic. Of course, a single 3V/5V supply may be used by
tying +V
S
and V
CC
together as well as GND and V
EE
.
The minimum voltage requirement can be simply stated
as both the output and the input stages need at least 2.7V
and the V
EE
pin must be equal to or less than ground.
The following rules must be adhered to in any confi guration:
2.7V ≤ (V
CC
– V
EE)
≤ 12V
2.7V ≤ (+V
S
– GND) ≤ 6V
(+V
S
– V
EE)
) ≤ 12V
V
EE
≤ Ground
Although the ground pin need not be tied to system ground,
most applications will use it that way. Figure 1 shows three
common confi gurations. The fi nal one is uncommon, but
it will work and may be useful as a level translator; the
input stage is run from –5.2V and ground while the output
stage is run from 3V and ground. In this case the com-
mon mode input voltage range does not include ground,
so it may be helpful to tie V
CC
to 3V. Conversely, V
CC
may
also be tied below ground, as long as the above rules are
not violated.
Input Voltage Considerations
The LT1715 is specifi ed for a common mode range of
–100mV to 3.8V when used with a single 5V supply. A
more general consideration is that the common mode
range is 100mV below V
EE
to 1.2V below V
CC
. The crite-
rion for this common mode limit is that the output still
responds correctly to a small differential input signal. If
one input is within the common mode limit, the other
input signal can go outside the common mode limits, up
to the absolute maximum limits, and the output will retain
the correct polarity.
When either input signal falls below the negative common
mode limit, the internal PN diode formed with the substrate
can turn on, resulting in signifi cant current fl ow through
the die. An external Schottky clamp diode between the
input and the negative rail can speed uprecovery from
negative overdrive by preventing the substrate diode from
turning on.
When both input signals are below the negative common
mode limit, phase reversal protection circuitry prevents
false output inversion to at least –400mV common mode.
However, the offset and hysteresis in this mode will increase
dramatically, to as much as 15mV each. The input bias
currents will also increase.
When one input signal goes above the common mode range
without exceeding a diode drop above the input supply rail,
the input stage will remain biased and the comparator will
maintain correct output polarity. Above this voltage, the
input stage current source will saturate completely and
the ESD protection diode will forward conduct. Once the
aberrant input falls back into the common mode range,
the comparator will respond correctly to valid input signals
within less than 10ns.
Figure 1. Variety of Power Supply Confi gurations
–
+
V
EE
V
CC
2.7V TO 6V
+V
S
GND
Single Supply
–
+
V
EE
V
CC
5V
–5V
3V
+V
S
GND
±5V Input, 3V Output Supplies
–
+
V
EE
V
CC
12V
5V
+V
S
GND
12V Input, 5V Output Supplies
–
+
V
EE
V
CC
–5.2V
3V
+V
S
GND
1715 F01
Front End Entirely Negative
APPLICATIONS INFORMATION
