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NCV51198PDR2G

P1-P3P4-P6P7-P9
© Semiconductor Components Industries, LLC, 2015
April, 2015 − Rev. 3
1 Publication Order Number:
NCP51198/D
NCP51198, NCV51198
1.5A DDR Memory
Termination Regulator
The NCP/NCV51198 is a simple, cost−effective, high−speed linear
regulator designed to generate the V
TT
termination voltage rail for
DDR−I, DDR−II and DDR−III memory. The regulator is capable of
actively sourcing or sinking up to ±1.5 A for DDR−I, or up to ±0.5 A
for DDR−II
/−III while regulating the output voltage to within
±30 mV.
The output termination voltage is tightly regulated to track V
TT
=
(V
DDQ
/ 2) over the entire current range.
The NCP/NCV51198 incorporates a high−speed differential
amplifier to provide ultra−fast response to line and load transients.
Other features include extremely low initial offset voltage, excellent
load regulation, source/sink soft−start and on−chip thermal shut−down
protection.
The NCP/NCV51198 features the power−saving Suspend To Ram
(STR) function which will tri−state the regulator output and lower the
quiescent current drawn when the /SS pin is pulled low.
The NCP/NCV51198 is available in a SOIC−8 Exposed Pad
package.
Features
• Generate DDR Memory Termination Voltage (V
TT
)
• For DDR−I, DDR−II, DDR−III Source / Sink Currents
• Supports DDR−I to ±1.5 A, DDR−II to ±0.5 A (peak)
• Integrated Power MOSFETs with Thermal Protection
• Stable with 10 mF Ceramic V
TT
Capacitor
• High Accuracy Output Voltage at Full−Load
• Minimal External Component Count
• Shutdown for Standby or Suspend to RAM (STR) mode
• Built−in Soft Start
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These are Pb−Free Devices
Appications
• Desktop PC’s, Notebooks, and Workstations
• Graphics Card DDR Memory Termination
• Set Top Boxes, Digital TV’s, Printers
• Embedded Systems
• Active Bus Termination
MARKING
DIAGRAM
www.
onsemi.com
SOIC8−NB EP
PD SUFFIX
CASE 751BU
V
DDQ
V
REF
18
PV
CC
V
TTS
V
CC
/SS
V
TT
GND
PIN CONNECTION
XXXXXX
AYWWG
G
XXXXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
SOIC−8 EP
1
8
See detailed ordering, marking and shipping information in the
package dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
NCP51198, NCV51198
www.onsemi.com
2
1.5 A, DDR−I /−II /−III TERMINATION REGULATOR
Figure 1. Typical Application Schematic
PIN FUNCTION DESCRIPTION – NCP51198
Pin Number
SO8−EP
Pin Name Pin Function
1 GND Common Ground.
2 /SS Suspend Shutdown supports Suspend To RAM function. CMOS compatible input sets V
TT
output to
high impedance state. Logic HI = Enable, Logic LO = Shutdown.
3 V
TTS
V
TTS
is the V
TT
sense input.
4 V
REF
V
REF
is an output pin that provides the buffered output of the internal reference voltage equal to half of
V
DDQ
. Two resistors dividing down the V
DDQ
voltage on the pin to create the regulated output voltage.
5 V
DDQ
The V
DDQ
pin is an input pin for creating the internal reference voltage to regulate V
TT
. The V
DDQ
volt-
age is connected to an internal resistor divider. The central tap of resistor divider (V
DDQ
/2) is con-
nected to the internal voltage buffer, which output is connected to V
REF
pin and the non−inverting input
of the error amplifier as the reference voltage.
6 V
CC
Power for the analog control circuitry.
7 PV
CC
The PV
CC
pin provides the rail voltage from where the V
TT
pin draws load current. There is a limitation
between V
CC
and PV
CC
. The PV
CC
voltage must be less or equal to the V
CC
voltage to ensure the
correct output voltage regulation. The V
TT
source current capability is dependent on PV
CC
voltage. The
higher the voltage on PV
CC
, the higher the source current.
8 V
TT
Regulator output voltage capable of sinking and sourcing current while regulating the output rail.
THERMAL
PAD
Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple
vias for maximum power dissipation performance.
NCP51198, NCV51198
www.onsemi.com
3
ABSOLUTE MAXIMUM RATINGS
Rating Symbol Value Unit
V
CC
, PV
CC
,V
DDQ
, /SS to GND (Note 1) −0.3 to +6 V
Storage Temperature T
stg
−65 to +150 °C
Operating Junction Temperature Range T
J
−40 to +125 °C
Thermal Characteristics, SO8−EP Thermal Resistance, Junction−to−Air
Power Rating at 25°C ambient = 2.3 W, derate 23 mW/°C
R
q
JA
43 °C/W
ESD Capability, Human Body Model (Note 2) ESD
HBM
2000 V
ESD Capability, Machine Model (Note 2) ESD
MM
150 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. No pin to exceed V
CC
. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following method:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
RECOMMENDED OPERATING CONDITIONS
Rating Symbol Value Unit
Bias Supply Voltage V
CC
2.2 to 5.5 V
Input Voltage PV
CC
1.35 to 2.5 V
Reference Input Voltage V
DDQ
1.35 to 2.7 V
ELECTRICAL CHARACTERISTICS
−40°C ≤ T
J
≤ 125°C; V
CC
= PV
CC
= V
DDQ
= 2.5 V; unless otherwise noted. Typical values are at T
J
= +25°C
Parameter
Condition Symbol Min Typ Max Unit
Reference Voltage (DDR I)
I
REF
= 0 mA (unloaded)
PV
CC
= V
DDQ
= 2.3 V
= 2.5 V
= 2.7 V
V
REF
(DDR−I)
1.125
1.225
1.325
1.151
1.251
1.351
1.175
1.275
1.375
V
Reference Voltage (DDR II)
I
REF
= 0 mA (unloaded)
PV
CC
= V
DDQ
= 1.7 V
= 1.8 V
= 1.9 V
V
REF
(DDR−II)
0.830
0.880
0.925
0.851
0.901
0.951
0.880
0.930
0.975
V
Reference Voltage (DDR III)
I
REF
= 0 mA (unloaded)
PV
CC
= V
DDQ
= 1.35 V
= 1.5 V
= 1.6 V
V
REF
(DDR−III)
0.660
0.735
0.785
0.676
0.751
0.801
0.695
0.770
0.820
V
V
REF
− Output Impedance
I
REF
= −30 mA to +30 mA
Z
REF
2.5
kW
V
TT
Output Voltage
(DDR−I)
I
OUT
= 0 A
PV
CC
= V
DDQ
= 2.3 V
PV
CC
= V
DDQ
= 2.5 V
PV
CC
= V
DDQ
= 2.7 V
V
TT
(DDR−I)
−
1.112
1.202
1.312
−
1.150
1.250
1.350
−
1.182
1.282
1.382
V
I
OUT
= +1.5 A
PV
CC
= V
DDQ
= 2.3V
PV
CC
= V
DDQ
= 2.5V
PV
CC
= V
DDQ
= 2.7V
V
TT
(DDR−I)
−
1.115
1.215
1.315
−
1.150
1.250
1.350
−
1.185
1.285
1.385
I
OUT
= −1.5 A
PV
CC
= V
DDQ
= 2.3V
PV
CC
= V
DDQ
= 2.5V
PV
CC
= V
DDQ
= 2.7V
V
TT
(DDR−I)
−
1.117
1.217
1.317
−
1.150
1.250
1.350
−
1.182
1.282
1.382
P1-P3P4-P6P7-P9

NCV51198PDR2G

Mfr. #:
Buy NCV51198PDR2G
Manufacturer:
ON Semiconductor
Description:
Linear Voltage Regulators 1.5ADDR MEMORY TERML REG
Lifecycle:
New from this manufacturer.
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