AD817
REV. B
–11–
A HIGH PERFORMANCE ADC INPUT BUFFER
High performance analog to digital converters (ADCs) require
input buffers with correspondingly high bandwidths and very
low levels of distortion. Typical requirements include distortion
levels of –60 dB to –70 dB for a 1 volt p-p signal and band-
widths of 10 MHz or more. In addition, an ADC buffer may
need to drive very large capacitive loads.
The circuit of Figure 36 is useful for driving high speed convert-
ers such as the differential input of the AD733, 10-bit ADC.
This circuit may be used with other converters with only minor
modifications. Using the AD817 provides the user with the op-
tion of either operating the buffer in differential mode or from a
single +5 volt supply. Operating from a +5 volt power supply
helps to avoid overdriving the ADC—a common problem with
buffers operating at higher supply voltages.
SINGLE SUPPLY OPERATION
Another exciting feature of the AD817 is its ability to perform
well in a single supply configuration. The AD817 is ideally
suited for applications that require low power dissipation and
high output current and those which need to drive large capaci-
tive loads, such as high speed buffering and instrumentation.
Referring to Figure 37, careful consideration should be given to
the proper selection of component values. The choices for this
particular circuit are: R1+ R3//R2 combine with C1 to form a
low frequency corner of approximately 300 Hz.
R2
10kΩ
C3
0.1µF
R1
9kΩ
R3
1kΩ
C2
0.1µF
C1
0.1µ F
C
L
200pF
R
L
150Ω
SELECT C1, R1, R2 & R3
FOR DESIRED LOW
FREQUENCY CORNER.
(R2 = R1 + R3)
C
OUT
+V
S
V
OUT
V
IN
AD817
7
6
3
2
4
0.01µF
3.3µF
Figure 37. Single Supply Amplifier Configuration
Combining R3 with C2 forms a low-pass filter with a corner
frequency of 1.5 kHz. This is needed to maintain amplifier
PSRR, since the supply is connected to V
IN
through the input
divider. The values for R
L
and C
L
were chosen to demonstrate
the AD817’s exceptional output drive capability. In this con-
figuration, the output is centered around 2.5 V. In order to
eliminate the static dc current associated with this level, C3 was
inserted in series with R
L
.
52.5Ω
0.1µF
1kΩ
0.1µF
–V
S
1kΩ
1kΩ
1kΩ
AD773
10-BIT
18MHz
ADC
V
INA
V
INB
ADREF43
VOLTAGE
REFERENCE
+2.5V
50Ω
COAX
CABLE
V
IN
500mVp-p
MAX
+V
S
AD817
7
6
3
2
4
26
27
0.1µF
0.1µF
–V
S
+V
S
AD817
7
6
3
2
4
+5V
COMMON
–5V
100µF
25V
100µF
25V
+V
S
–V
S
Figure 36. A Differential Input Buffer for High Bandwidth ADCs
