ZL30109 Data Sheet
13
Zarlink Semiconductor Inc.
Figure 6 - E1 Mode Out-of-Range Limits (OOR_SEL=1)
3.3 Time Interval Error (TIE) Corrector Circuit
The TIE corrector circuit eliminates phase transients on the output clock that may occur during reference switching
or the recovery from Holdover mode to Normal mode.
On recovery from Holdover mode (dependent on the HMS pin) or when switching to another reference input, the
TIE corrector circuit measures the phase delay between the current phase (feedback signal) and the phase of the
selected reference signal. This delay value is stored in the TIE corrector circuit. This circuit creates a new virtual
reference signal that is at the same phase position as the feedback signal. By using the virtual reference, the PLL
minimizes the phase transient it experiences when it switches to another reference input or recovers from Holdover
mode.
The delay value can be reset by setting the TIE corrector circuit Clear pin (TIE_CLR
) low for at least 15 ns. This
results in a phase alignment between the input reference signal and the output clocks and frame pulses as shown
in Figure 16 and Figure 17. The speed of the phase alignment correction is limited to 61 μs/s when BW_SEL=0.
Convergence is always in the direction of least phase travel. In general the TIE correction should not be exercised
when Holdover mode is entered for short time periods. TIE_CLR
can be kept low continuously; in that case the
output clocks will always be aligned with the selected input reference. This is illustrated in Figure 7.
0 ppm
+50 ppm
-50 ppm
0
80
130100
C20
C20
50
50-50-150
-150 -100 0-200 -50 50 150 200
Frequency
Out of Range
Out of Range
Out of Range
In Range
In Range
In Range
Offset [ppm]
0
0
C20
100
-100-130
180150-50-80
-180
C20: 20 MHz master clock on OSCi
C20 Clock Accuracy
