EZAIRO 7111 HYBRID
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12
ARCHITECTURE OVERVIEW
The Ezairo 7100 system is an asymmetric quad−core
architecture, mixed−signal system−on−chip designed
specifically for audio processing. It centers around four
processing cores: the CFX Digital Signal Processor (DSP),
the HEAR Configurable Accelerator, the Arm Cortex−M3
Processor Subsystem, and the Filter Engine.
CFX DSP Core
The CFX DSP core is used to configure the system and the
other cores, and it coordinates the flow of signal data
progressing through the system. The CFX DSP can also be
used for custom signal processing applications that can’t be
handled by the HEAR or the Filter Engine.
The CFX DSP is a user−programmable general−purpose
DSP core that uses a 24−bit fixed−point, dual−MAC,
dual−Harvard architecture. It is able to perform two MACs,
two memory operations and two pointer updates per cycle,
making it well−suited to computationally intensive
algorithms.
The CFX features:
• Dual−MAC 24−bit load−store DSP core
• Four 56−bit accumulators
• Four 24−bit input registers
• Support for hardware loops nested up to four deep
• Combined XY memory space (48 bits wide)
• Dual address generator units
• A wide range of addressing modes:
− Direct
− Indirect with post−modification
− Modulo addressing
− Bit reverse
For further information on the usage of the CFX DSP,
please refer to the Hardware Reference Manual and to the
CFX DSP Architecture Manual available in the Ezairo 7100
Evaluation and Development Kit (EDK).
HEAR Configurable Accelerator
The HEAR coprocessor is designed to perform both
common signal processing operations and complex standard
filterbanks such as the WOLA filterbank, reducing the load
on the CFX DSP core.
The HEAR Configurable Accelerator is a highly
optimized signal processing engine that is configured
through the CFX. It offers high speed, high flexibility and
high performance, while maintaining low power
consumption. For added computing precision, the HEAR
supports block floating point processing. Configuration of
the HEAR is performed using the HEAR configuration tool
(HCT). For further information on the usage of the HEAR,
please refer to the HEAR Configurable Accelerator
Reference Manual available in the Ezairo 7100 EDK.
The HEAR is optimized for advanced hearing aid
algorithms including but not limited to the following:
• Dynamic range compression
• Directional processing
• Feedback cancellation
• Noise reduction
To execute these and other algorithms efficiently, the
HEAR excels at the following:
• Processing using a weighted overlap add (WOLA)
filterbank
• Time domain filtering
• Subband filtering
• Attack/release filtering
• Vector addition/subtraction/multiplication
• Signal statistics (such as average, variance and
correlation)
Arm Cortex−M3 Processor Subsystem
The Arm Cortex−M3 Processor Subsystem provides
support for data transfer to and from the wireless transceiver.
The subsystem includes hardwired CODECS (G.722,
CVSD), Error Correction support (Reed−Solomon,
Hamming), interfaces (SPI, I
2
C, PCM, GPIOs), as well as an
open−programmable Arm Cortex−M3 processor.
Arm Cortex−M3 Processor
The Arm Cortex−M3 processor is a low−power processor
that features low gate count, low interrupt latency, and
low−cost debugging. It is intended for deeply embedded
applications that require fast interrupt response features.
GNU tools provide build and link support C programs that
run on the Arm Cortex−M3 processor.
Filter Engine
The Filter Engine is a core that provides low−delay path
and basic filtering capabilities for the Ezairo 7100 system.
The Filter Engine can implement filters (either FIR or IIR)
with a total of up to 160 coefficients. FIR filters are
implemented using a direct−form structure. IIR filters are
implemented with a cascade of second−order sections
(biquads), each implemented as a direct−form I filter.
The Filter Engine is programmable, but does not include
direct debugging access. The CFX can monitor the Filter
Engine state through control and configuration registers on
the program memory bus.
Digital Input/Output (DIO) Pads
A total of 5 DIOs are available on the Ezairo 7111 hybrid.
These pads can all be configured for a variety of digital input
and output modes or as LSADs. The user can configure
DIOs signal to be, for example:
• CFX PCM interface
• CFX UART interface
• CFX SPI interface
• LSAD input
• GPIOs data for the CFX
