AD9573
Rev. 0 | Page 6 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
VDDA
VDDX
XO1
7
8
G
NDA
VDDA
GNDX
XO2
GNDA
16
15
14
13
12
11
GND
100M
100M
VDD33
VDD
OE
TOP VIEW
(Not to Scale)
AD9573
10
9
33M
GND33
07500-005
Figure 5. Pin Configuration
Table 10. Pin Function Descriptions
Pin No. Mnemonic Description
1, 7 GNDA Analog Ground.
2, 8 VDDA Analog Power Supply (3.3 V).
3 VDDX
Crystal Oscillator Power Supply.
4, 5 XO1, XO2
External 25 MHz Crystal.
6 GNDX
Crystal Oscillator Ground.
9 GND33
Ground for LVCMOS Output.
10 33M
LVCMOS Output at 33.33 MHz.
11 VDD33
Power Supply for LVCMOS Output.
12 VDD
Power Supply for LVDS Output.
13
100M
Complementary LVDS Output at 100 MHz.
14 100M
LVDS Output at 100 MHz.
15 GND
Ground for LVDS Output.
16
OE Output Enable (Active Low). Places both outputs in a high impedance state when high. This pin has a 50 kΩ
internal pull-down resistor.
AD9573
Rev. 0 | Page 7 of 12
07500-006
TYPICAL PERFORMANCE CHARACTERISTICS
115
–145
–135
–125
–120
–150
–140
–130
PHASE NOISE (dBc/Hz)
–155
1k 10k 100k 1M 10M 100M
FREQUENCY OFFSET (Hz)
Figure 6. 100 MHz Phase Noise
0750
120
–130
–140
–150
–160
1k 10k 100k 1M 10M 100M
PHASE NOISE (dBc/Hz)
FREQUENCY OFFSET (Hz)
0-007
Figure 7. 33.33 MHz Phase Noise
AD9573
Rev. 0 | Page 8 of 12
TERMINOLOGY
Phase Jitter
An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0 degrees to
360 degrees for each cycle. Actual signals, however, display a
certain amount of variation from ideal phase progression over
time. This phenomenon is called phase jitter. Although many
causes can contribute to phase jitter, one major cause is random
noise, which is characterized statistically as gaussian (normal)
in distribution.
This phase jitter leads to a spreading out of the energy of the
sine wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as
a series of values whose units are dBc/Hz at a given offset in
frequency from the sine wave (carrier). The value is a ratio
(expressed in dB) of the power contained within a 1 Hz
bandwidth with respect to the power at the carrier frequency.
For each measurement, the offset from the carrier frequency is
also given.
Phase Noise
When the total power contained within some interval of offset
frequencies (for example, 12 kHz to 20 MHz) is integrated, it is
called the integrated phase noise over that frequency offset
interval, and it can be readily related to the time jitter due to the
phase noise within that offset frequency interval.
Phase noise has a detrimental effect on error rate performance
by increasing eye closure at the transmitter output and reducing
the jitter tolerance/sensitivity of the receiver.
Time Jitter
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When observing
a sine wave, the time of successive zero crossings is seen to vary.
In a square wave, the time jitter is seen as a displacement of the
edges from their ideal (regular) times of occurrence. In both
cases, the variations in timing from the ideal are the time jitter.
Because these variations are random in nature, the time jitter is
specified in units of seconds root mean square (rms) or 1 sigma
of the gaussian distribution.
Additive Phase Noise
Additive phase noise is the amount of phase noise that is
attributable to the device or subsystem being measured. The
phase noise of any external oscillators or clock sources has been
subtracted. This makes it possible to predict the degree to which
the device impacts the total system phase noise when used in
conjunction with the various oscillators and clock sources, each
of which contributes its own phase noise to the total. In many
cases, the phase noise of one element dominates the system
phase noise.
Additive Time Jitter
Additive time jitter is the amount of time jitter that is
attributable to the device or subsystem being measured. The
time jitter of any external oscillators or clock sources has been
subtracted. This makes it possible to predict the degree to which
the device impacts the total system time jitter when used in
conjunction with the various oscillators and clock sources, each
of which contributes its own time jitter to the total. In many
cases, the time jitter of the external oscillators and clock sources
dominates the system time jitter.

AD9573ARUZ-RL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Clock Generators & Support Products PCI-Express PLL Core 2 Outputs
Lifecycle:
New from this manufacturer.
Delivery:
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