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CY2314ANZSXC-1

P1-P3P4-P6P7-P8
CY2314ANZ
Document #: 38-07143 Rev. *B Page 4 of 8
Switching Characteristics
[4]
Over the Operating Range
Parameter Name Test Conditions Min Typ Max Unit
Maximum Operating Frequency 100 MHz
Duty Cycle
[3, 5]
= t
2
÷ t
1
Measured at 1.5V 45.0 50.0 55.0 %
t
3
Rising Edge Rate
[3]
Measured between 0.4V and 2.4V 0.9 1.5 4.0 V/ns
t
4
Falling Edge Rate
[3]
Measured between 2.4V and 0.4V 0.9 1.5 4.0 V/ns
t
5
Output to Output Skew
[3]
All outputs equally loaded –250 +250 ps
t
6
SDRAM Buffer LH Propogation
Delay
[3]
Input edge greater than 1 V/ns 1.0 3.5 5.0 ns
t
7
SDRAM Buffer HL Propogation
Delay
[3]
Input edge greater than 1 V/ns 1.0 3.5 5.0 ns
t
8
SDRAM Buffer Enable Delay
[3]
Input edge greater than 1 V/ns 1.0 5 12 ns
t
9
SDRAM Buffer Disable Delay
[3]
Input edge greater than 1 V/ns 1.0 20 30 ns
Switching Waveforms
Figure 2. Duty Cycle Timing
Figure 3. All Outputs Rise/Fall Time
Figure 4. Output-Output Skew
t
1
t
2
1.5V 1.5V 1.5V
OUTPUT
t
3
3.3V
0V
0.4V
2.4V 2.4V
0.4V
t
4
1.5V
t
5
OUTPUT
OUTPUT
1.5V
Notes
4. All parameters specified with loaded outputs.
5. Duty cycle of input clock is 50%. Rising and falling edge rate of the input clock is greater than 1 V/ns.
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CY2314ANZ
Document #: 38-07143 Rev. *B Page 5 of 8
Test Circuit
Figure 5. SDRAM Buffer LH and HL Propagataion Delay
Figure 6. SDRAM Buffer Enable and Disable Times
Switching Waveforms
(continued)
t
6
INPUT
OUTPUT
t
7
t
8
OE
OUTPUTS
t
9
Three-State
Active
0.1 μF
V
DD
CLK out
C
LOAD
OUTPUTS
GND
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CY2314ANZ
Document #: 38-07143 Rev. *B Page 6 of 8
Application Information
Clock traces must be terminated with either series or parallel termination, as is normally done.
Recommendation
■
Surface mount, low ESR,and ceramic capacitors must be used for filtering. Typically, these capacitors have a value of 0.1 μF. In
some cases, smaller value capacitors may be required.
■
The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of
the trace, Rout is the output impedance of the buffer (typically 25Ω), and Rseries is the series terminating resistor.
Rseries > Rtrace – Rout
■
Footprints must be laid out for optional EMI reducing capacitors, which should be placed as close to the terminating resistor as is
physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF.
■
A ferrite bead may be used to isolate the board V
DD
from the clock generator V
DD
island. Ensure that the ferrite bead offers greater
than 50Ω impedance at the clock frequency, under loaded DC conditions. Refer to the application note Layout and Termination
Techniques for Cypress Clock Generators for more details.
■
If a ferrite bead is used, a 10 μF to 22 μF tantalum bypass capacitor should be placed close to the ferrite bead. This capacitor
prevents power supply droop during current surges.
Figure 7. Application Circuit
C
d
= DECOUPLING CAPACITORS
C
t
= OPTIONAL EMI- REDUCING CAPACITORS
R
s
= SERIES TERMINATING RESISTORS
CY 2314 28 Pin SOIC
C
d
0.1uF
V
DD
3.3V
V
SS
BUF_IN
V
DD
C
t
SDRAM (0-13)
SDRAM (0-13)
SDATA
SCLK
R
s
SDATA
SCLK
CPUCLK
PCICLK
USBCLK
REF
APIC
R
s
* This Frequency Synthesizer is used to generate
CPU, PCI, USB, REF, and APIC Clocks
* CY2280 48 Pin SSOP
(or CY2281 or CY2282)
Ordering Information
Ordering Code
Package
Name
Package Type
Operating
Range
Pb-Free
CY2314ANZSXC-1 SZ283 28-Pin SOIC Commercial
CY2314ANZSXC-1T SZ283 28-Pin SOIC - Tape and Reel Commercial
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P1-P3P4-P6P7-P8

CY2314ANZSXC-1

Mfr. #:
Buy CY2314ANZSXC-1
Manufacturer:
Cypress Semiconductor
Description:
Clock Buffer 3.3V Buffer COM
Lifecycle:
New from this manufacturer.
Delivery:
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