Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XR16M570
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
DECEMBER 2009 REV. 1.0.1
GENERAL DESCRIPTION
The XR16M570
1
(M570) is an enhanced Universal
Asynchronous Receiver and Transmitter (UART) with
16 bytes of transmit and receive FIFOs, selectable
transmit and receive FIFO trigger levels, automatic
hardware and software flow control, and data rates of
up to 16 Mbps at 3.3V, 12.5 Mbps at 2.5V and 7.5
Mbps at 1.8V with 4X data sampling rate.
The Auto RS-485 Half-Duplex Direction control
feature simplifies both the hardware and software for
half-duplex RS-485 applications. In addition, the
Multidrop mode with Auto Address detection
increases the performance by simplifying the
software routines.
The Independent TX/RX Baud Rate Generator
feature allows the transmitter and receiver to operate
at different baud rates. Power consumption of the
M570 can be minimized by enabling the sleep mode
and PowerSave mode.
The M570 has a 16550 compatible register set that
provide users with operating status and control,
receiver error indications, and modem serial interface
controls. An internal loopback capability allows
onboard diagnostics. The M570 is available in 24-pin
QFN, 32-pin QFN and 25-pin BGA packages. All
three packages offer the 16 mode (Intel bus) interface
only.
NOTE: 1 Covered by U.S. Patent #5,649,122.
FEATURES
Pin-to-pin compatible with XR16L570 in 24-QFN
and 32-QFN packages
Intel data bus Interface
16 Mbps maximum data rate
Selectable TX/RX FIFO Trigger Levels
TX/RX FIFO Level Counters
Independent TX/RX Baud Rate Generator
Fractional Baud Rate Generator
Auto RTS/CTS Hardware Flow Control
Auto XON/XOFF Software Flow Control
Auto RS-485 Half-Duplex Direction Control
Multidrop mode w/ Auto Address Detect
Sleep Mode with Automatic Wake-up
PowerSave mode in 24-pin QFN package
Infrared (IrDA 1.0 and 1.1) mode
1.62V to 3.63V supply operation
Crystal oscillator or external clock input
APPLICATIONS
Personal Digital Assistants (PDA)
Cellular Phones/Data Devices
Battery-Operated Devices
Global Positioning System (GPS)
Bluetooth
F
IGURE 1. XR16M570 BLOCK DIAGRAM
VCC
XTAL1
XTAL2
Crystal Osc/Buffer
TX, RX,
RTS#, CTS#,
DTR#, DSR#,
Intel
Data Bus
Interface
UART
16 Byte RX FIFO
BRG
IR
ENDEC
TX &
RX
UART
Regs
A2:A0
PwrSave
16 Byte TX FIFO
RI#, CD#
RESET
D7:D0
IOW#
CS#
INT
IOR#
GND
(1.62 to 3.63 V)
XR16M570
2
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.1
FIGURE 2. PIN OUT ASSIGNMENT FOR 24-PIN QFN, 32-PIN QFN AND 25-BGA PACKAGES
ORDERING INFORMATION
PART NUMBER PACKAGE
OPERATING TEMPERATURE
RANGE
DEVICE STATUS
XR16M570IL24 24-Pin QFN -40°C to +85°C Active
XR16M570IL32 32-Pin QFN -40°C to +85°C Active
XR16M570IB25 25-Pin BGA -40°C to +85°C Active
24-pin QFN
123456
11
12
7
10
8
9
18 17 16 15 14 13
20
19
24
21
23
22
D7
RX
TX
CS#
D6
D5
RTS#
INT
A0
A1
Reset
CTS#
D2
D1
D0
VCC
D3
D4
IOW#
GND
IOR#
A2
CLK
PwrSave
1
23456
78
24
23
22 21 20 19
18
17
32
31
30
29
28
27
26
25
11
12
13
14
15
16
9
10
1
2
#
#
RI#
D3
D2
D1
D0
VCC
DSR#
CD#
XTAL
XTAL
IOW
GND
IOR
NC
NC
NC
D6
D7
RX
TX
CS
D4
D5
NC
32-pin QFN
RESET
RTS#
INT
DTR#
A0
A1
A2
CTS#
1 2 3 4 5
A
B
C
D
E
Transparent Top View
A1 Corner
CTS# RESET INT A1 A2
VCC DTR# RTS# A0 IOR#
D0 D6 D7 DSR# IOW#
D3 D1 TX CS# XTAL1
D4 D2 D5 RX GND
XR16M570
3
REV. 1.0.1 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
PIN DESCRIPTIONS
Pin Description
NAME
24-QFN
P
IN#
32-QFN
PIN#
25-BGA
PIN#
T
YPE DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
12
13
14
17
18
19
A5
A4
B4
I
Address lines [2:0]. These 3 address lines select the internal regis-
ters in UART during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
3
2
1
24
23
22
21
20
5
4
3
1
32
31
30
29
C3
C2
E3
E1
D1
E2
D2
C1
I/O
Data bus lines [7:0] (bidirectional).
IOR# 11 14 B5 I
This input is read strobe (active low). The falling edge instigates an
internal read cycle and retrieves the data byte from an internal reg-
ister pointed by the address lines [A2:A0], puts the data byte on the
data bus to allow the host processor to read it on the rising edge.
IOW# 9 12 C5 I
This input is write strobe (active low). The falling edge instigates the
internal write cycle and the rising edge transfers the data byte on
the data bus to an internal register pointed by the address lines.
CS# 6 8 D4 I
This input is chip select (active low) to enable the device.
INT 15 20 A3 O
This output is the active high device interrupt output. The output
state is defined by the user through the software setting of MCR[3].
INT is set to the active mode when MCR[3] is set to a logic 1. INT is
set to the three state mode when MCR[3] is set to a logic 0. See
MCR[3].
MODEM OR SERIAL I/O INTERFACE
TX 5 7 D3 O
UART Transmit Data or infrared encoder data. Standard transmit
and receive interface is enabled when MCR[6] = 0. In this mode,
the TX signal will be a logic 1 during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In
the Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0. If it is not used, leave it
unconnected.
RX 4 6 E4 I
UART Receive Data or infrared receive data. Normal receive data
input must idle at logic 1 condition. The infrared receiver idles at
logic 0. This input should be connected to VCC when not used.
RTS# 16 21 B3 O
UART Request-to-Send (active low) or general purpose output.
This output must be asserted prior to using auto RTS flow control,
see EFR[6], MCR[1] and IER[6].
CTS# 18 24 A1 I
UART Clear-to-Send (active low) or general purpose input. It can
be used for auto CTS flow control, see EFR[7], MSR[4] and IER[7].
This input should be connected to VCC when not used.
DTR# - 22 B2 O
UART Data-Terminal-Ready (active low) or general purpose output.

XR16M570IL24-0C-EB

Mfr. #:
Manufacturer:
MaxLinear
Description:
Interface Development Tools Eval Board for XR16M570IL24 Series
Lifecycle:
New from this manufacturer.
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