4
FN9240.2
November 10, 2015
Absolute Maximum Ratings Thermal Information
Supply Voltage (VCC, VCTRL) . . . . . . . . . . . . . . . . . . . -0.3V to 7V
Input Voltage (V
EN
, V
PWM
) . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
BOOT Voltage (V
BOOT-GND
). . . -0.3V to 25V (DC) or 36V (<200ns)
BOOT To PHASE Voltage (V
BOOT-PHASE
) . . . . . . -0.3V to 7V (DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 9V (<10ns)
PHASE Voltage . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V (DC)
. . . . . . . . . GND -8V (<20ns Pulse Width, 10µJ) to 30V (<100ns)
UGATE Voltage . . . . . . . . . . . . . . . . V
PHASE
- 0.3V (DC) to V
BOOT
. . . . . . . . . . . V
PHASE
- 5V (<20ns Pulse Width, 10µJ) to V
BOOT
LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V
. . . . . . . . . . GND - 2.5V (<20ns Pulse Width, 5µJ) to VCC + 0.3V
Ambient Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +125°C
HBM ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Thermal Resistance
JA
(°C/W)
JC
(°C/W)
SOIC Package (Note 1) . . . . . . . . . . . . 110 N/A
DFN Package (Notes 2, 3) . . . . . . . . . . 48 7
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +100°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . . +125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V 10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
3.
JC
, "case temperature" location is at the center of the package underside exposed pad. See Tech Brief TB379 for details.
Electrical Specifications These specifications apply for “Recommended Operating Conditions” on page 4, unless otherwise
noted.
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 5) TYP
MAX
(Note 5) UNITS
VCC SUPPLY CURRENT
Bias Supply Current I
VCC
PWM pin floating, V
VCC
= 5V - 190 - µA
POR Rising -3.44.2
POR Falling 2.2 3.0 -
Hysteresis - 400 - mV
VCTRL INPUT
Rising Threshold - 2.75 2.90 V
Falling Threshold 2.4 2.65 - V
PWM INPUT
Sinking Impedance R
PWM_SNK
-3.5- k
Source Impedance R
PWM_SRC
-3.5- k
Tri-State LowerThreshold V
VCTRL
= 3.3V (-110mV Hysteresis) - 1.1 - V
V
VCTRL
= 5V (-250mV Hysteresis) - 1.5 - V
Tri-State Upper Threshold V
VCTRL
= 3.3V (+110mV Hysteresis) - 1.9 - V
V
VCTRL
= 5V (+250mV Hysteresis) - 3.25 - V
Tri-State Shutdown Holdoff Time t
TSSHD
t
PDLU
or t
PDLL
+ Gate Falling Time - 20 - ns
SWITCHING TIME (See Figure 1 on page 6)
UGATE Rise Time (Note 4) t
RU
V
VCC
= 5V, 3nF Load - 8.0 - ns
LGATE Rise Time (Note 4) t
RL
V
VCC
= 5V, 3nF Load - 8.0 - ns
UGATE Fall Time (Note 4) t
FU
V
VCC
= 5V, 3nF Load - 8.0 - ns
LGATE Fall Time (Note 4) t
FL
V
VCC
= 5V, 3nF Load - 4.0 - ns
UGATE Turn-Off Propagation Delay t
PDLU
V
VCC
= 5V, Outputs Unloaded - 20 - ns
LGATE Turn-Off Propagation Delay t
PDLL
V
VCC
= 5V, Outputs Unloaded - 15 - ns
UGATE Turn-On Propagation Delay t
PDHU
V
VCC
= 5V, Outputs Unloaded - 19 - ns
ISL6596
5
FN9240.2
November 10, 2015
LGATE Turn-On Propagation Delay t
PDHL
V
VCC
= 5V, Outputs Unloaded - 18 - ns
Tri-state to UG/LG Rising Propagation Delay t
PTS
V
VCC
= 5V, Outputs Unloaded - 30 - ns
OUTPUT (Note 4)
Upper Drive Source Resistance R
UG_SRC
250mA Source Current - 1.0 2.5
Upper Drive Sink Resistance R
UG_SNK
250mA Sink Current - 1.0 2.5
Lower Drive Source Resistance R
LG_SRC
250mA Source Current - 1.0 2.5
Lower Drive Sink Resistance R
LG_SNK
250mA Sink Current - 0.4 1.0
NOTES:
4. Limits established by characterization and are not production tested.
5. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Electrical Specifications These specifications apply for “Recommended Operating Conditions” on page 4, unless otherwise
noted. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 5) TYP
MAX
(Note 5) UNITS
ISL6596
6
FN9240.2
November 10, 2015
Functional Pin Description
Note: Pin numbers refer to the SOIC package. Check
diagram for corresponding DFN pinout.
UGATE (Pin 1)
Upper gate drive output. Connect to gate of high-side
N-Channel power MOSFET. A gate resistor is never
recommended on this pin, as it interferes with the operation
shoot-through protection circuitry.
BOOT (Pin 2)
Floating bootstrap supply pin for the upper gate drive.
Connect a bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge
used to turn on the upper MOSFET. See “Bootstrap
Considerations” on page 7 for guidance in choosing the
appropriate capacitor value.
PWM (Pin 3)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation, see
“PWM Input and Threshold Control” on page 7 for further
details. Connect this pin to the PWM output of the controller.
GND (Pin 4)
Ground pin. All signals are referenced to this node.
LGATE (Pin 5)
Lower gate drive output. Connect to gate of the low side
N-Channel power MOSFET. A gate resistor is never
recommended on this pin, as it interferes with the operation
shoot-through protection circuitry.
VCC (Pin 6)
Connect this pin to a +5V bias supply. Locally bypass with a
high quality ceramic capacitor to ground.
VCTRL (Pin 7)
This pin sets the PWM logic threshold. Connect this pin to
3.3V source for 3.3V PWM input and pull it to 5V source for
5V PWM input.
PHASE (Pin 8)
Connect this pin to the source of the upper MOSFET. This
pin provides the return path for the upper gate driver current.
Thermal Pad (in DFN only)
The metal pad underneath the center of the IC is a thermal
substrate. The PCB “thermal land” design for this exposed
die pad should include vias that drop down and connect to
one or more buried copper plane(s). This combination of
vias for vertical heat escape and buried planes for heat
spreading allows the DFN to achieve its full thermal
potential. This pad should be either grounded or floating,
and it should not be connected to other nodes. Refer to
TB389 for design guidelines.
Timing Diagram
PWM
UGATE
LGATE
t
PDLL
t
PDHU
t
RU
t
PDLU
t
PDHL
t
RL
1V
t
RU
t
FU
t
FL
1V
t
PTS
t
TSSHD
t
TSSHD
t
PTS
FIGURE 1. TIMING DIAGRAM
50% of VCC
ISL6596

ISL6596CRZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Gate Drivers SYNCHCT BUCK MSFT METAL OPTION
Lifecycle:
New from this manufacturer.
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